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| Presentation | 2022-11-28 15:25 A 6T-8T hybrid SRAM for reducing the power of neural network by lowing the operating voltage Ruoxi Yu, Kazuteru Namba (Chiba Univ.)  VLD2022-24 ICD2022-41 DC2022-40 RECONF2022-47 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | With advances in artificial intelligence and machine learning technologies, many deep learning applications are being deployed in embedded systems and mobile devices. However, deployment in these devices is limited by high memory power consumption. Lowering the operating voltage of the SRAM used in the neural network can reduce the power consumption of the neural network. However, lowering the operating voltage of SRAM increases the bit error rate (BER) of the circuit. Therefore, SRAM 8T cells have a higher static noise margin (SNM) than conventional 6T cells, and the BER of 8T cells is lower than that of 6T cells, even if the same width lowers the operating voltage. In this research, based on the relationship between the BER of SRAM and the classification accuracy of neural networks, we investigate the relationship between the two. We propose a 6T-8T hybrid SRAM circuit by combining conventional 6T SRAM cells and 8T SRAM cells. This hybrid SRAM reduces the power consumption of neural networks by operating at a lower operating voltage than conventional SRAM. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | SRAM / Neural Network / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 122, no. 285, DC2022-40, pp. 31-36, Nov. 2022. | |
| Paper # | DC2022-40 | |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2022-24 ICD2022-41 DC2022-40 RECONF2022-47 |
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| Conference Information | |
| Committee | VLD DC RECONF ICD IPSJ-SLDM |
| Conference Date | 2022-11-28 - 2022-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2022 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2022-11-VLD-DC-RECONF-ICD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 6T-8T hybrid SRAM for reducing the power of neural network by lowing the operating voltage |
| Sub Title (in English) | |
| Keyword(1) | SRAM |
| Keyword(2) | Neural Network |
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| 1st Author's Name | Ruoxi Yu |
| 1st Author's Affiliation | Chiba University (Chiba Univ.) |
| 2nd Author's Name | Kazuteru Namba |
| 2nd Author's Affiliation | Chiba University (Chiba Univ.) |
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| Speaker | Author-1 |
| Date Time | 2022-11-28 15:25:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | VLD2022-24, ICD2022-41, DC2022-40, RECONF2022-47 |
| Volume (vol) | vol.122 |
| Number (no) | no.283(VLD), no.284(ICD), no.285(DC), no.286(RECONF) |
| Page | pp.31-36 |
| #Pages | 6 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |
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