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| Presentation | 2022-11-28 15:00 On reduction of test patterns for a Multiplier Using Approximate Computing Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ)  VLD2022-23 ICD2022-40 DC2022-39 RECONF2022-46 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In recent years, approximate computing has been used in error-tolerant applications. Several approximation methods have been proposed for approximate multipliers by truncating the lower bits of the calculation result according to the positions of one-bits in the multiplier and the multiplicand. In testing approximation circuits, test time reduction can possibly be achieved by removing faults that affect only within the acceptable range of the calculation error. In this paper, to generate fewer test patterns for an approximate multiplier, the pseudo circuit restricting the fault propagation only to the lower bits is added in the test generation phase. As a result, the proposed test generation can attain about a 19.8% reduction in test patterns. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | test pattern generation / approximate computing / multiplier / test time reduction / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 122, no. 285, DC2022-39, pp. 25-30, Nov. 2022. | |
| Paper # | DC2022-39 | |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2022-23 ICD2022-40 DC2022-39 RECONF2022-46 |
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| Conference Information | |
| Committee | VLD DC RECONF ICD IPSJ-SLDM |
| Conference Date | 2022-11-28 - 2022-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2022 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2022-11-VLD-DC-RECONF-ICD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On reduction of test patterns for a Multiplier Using Approximate Computing |
| Sub Title (in English) | |
| Keyword(1) | test pattern generation |
| Keyword(2) | approximate computing |
| Keyword(3) | multiplier |
| Keyword(4) | test time reduction |
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| 1st Author's Name | Shogo Tokai |
| 1st Author's Affiliation | Tokushima University (Tokushima Univ) |
| 2nd Author's Name | Daichi Akamatsu |
| 2nd Author's Affiliation | Tokushima University (Tokushima Univ) |
| 3rd Author's Name | Hiroyuki Yotsuyanagi |
| 3rd Author's Affiliation | Tokushima University (Tokushima Univ) |
| 4th Author's Name | Masaki Hashizume |
| 4th Author's Affiliation | Tokushima University (Tokushima Univ) |
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| Speaker | Author-1 |
| Date Time | 2022-11-28 15:00:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | VLD2022-23, ICD2022-40, DC2022-39, RECONF2022-46 |
| Volume (vol) | vol.122 |
| Number (no) | no.283(VLD), no.284(ICD), no.285(DC), no.286(RECONF) |
| Page | pp.25-30 |
| #Pages | 6 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |
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