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| Presentation | 2022-11-30 09:55 Design of Digital Phase-Locked Loop Circuit based on 3rd-Order MASH ΔΣ FDC for Low In-Band Phase Noise Ryoga Iwashita, Zule Xu, Masaru Osada, Ryoya Shibata, Yo Kumano, Tetsuya Iizuka (UTokyo)  VLD2022-43 ICD2022-60 DC2022-59 RECONF2022-66 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | $DeltaSigma$ frequency-to-digital converter based phase locked loops (FDC-PLLs) can reduce its quantization noise at low frequency by $DeltaSigma$ modulation. However, it requires narrow PLL bandwidth. This paper proposes the method to design higher-order $DeltaSigma$ FDC-PLLs by applying multi-stage noise shaping (MASH). The proposed PLLs can make in-band quantization noise lower than that of conventional FDC-PLLs , which enables more flexible loop optimization. The proposed PLL is designed in 65,nm CMOS process using 3bit SAR ADC and a $DeltaSigma$ ADC. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Phase locked loop(PLL) / $DeltaSigma$ frequency-to-digital converter(FDC) / multi-stage noise shaping(MASH) / quantization noise / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 122, no. 284, ICD2022-60, pp. 138-143, Nov. 2022. | |
| Paper # | ICD2022-60 | |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2022-43 ICD2022-60 DC2022-59 RECONF2022-66 |
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| Conference Information | |
| Committee | VLD DC RECONF ICD IPSJ-SLDM |
| Conference Date | 2022-11-28 - 2022-11-30 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2022 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2022-11-VLD-DC-RECONF-ICD-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Digital Phase-Locked Loop Circuit based on 3rd-Order MASH ΔΣ FDC for Low In-Band Phase Noise |
| Sub Title (in English) | |
| Keyword(1) | Phase locked loop(PLL) |
| Keyword(2) | $DeltaSigma$ frequency-to-digital converter(FDC) |
| Keyword(3) | multi-stage noise shaping(MASH) |
| Keyword(4) | quantization noise |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Ryoga Iwashita |
| 1st Author's Affiliation | The University of Tokyo (UTokyo) |
| 2nd Author's Name | Zule Xu |
| 2nd Author's Affiliation | The University of Tokyo (UTokyo) |
| 3rd Author's Name | Masaru Osada |
| 3rd Author's Affiliation | The University of Tokyo (UTokyo) |
| 4th Author's Name | Ryoya Shibata |
| 4th Author's Affiliation | The University of Tokyo (UTokyo) |
| 5th Author's Name | Yo Kumano |
| 5th Author's Affiliation | The University of Tokyo (UTokyo) |
| 6th Author's Name | Tetsuya Iizuka |
| 6th Author's Affiliation | The University of Tokyo (UTokyo) |
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| Speaker | Author-1 |
| Date Time | 2022-11-30 09:55:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | VLD2022-43, ICD2022-60, DC2022-59, RECONF2022-66 |
| Volume (vol) | vol.122 |
| Number (no) | no.283(VLD), no.284(ICD), no.285(DC), no.286(RECONF) |
| Page | pp.138-143 |
| #Pages | 6 |
| Date of Issue | 2022-11-21 (VLD, ICD, DC, RECONF) |
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