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Paper Abstract and Keywords
Presentation 2022-11-30 14:20
On the performance evaluation of a PUF circuit using the Delay Testable Circuit under temperature effects
Eisuke Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2022-46 ICD2022-63 DC2022-62 RECONF2022-69
Abstract (in Japanese) (See Japanese page) 
(in English) In this study, we have proposed a method to make the design-for-testability circuity function as a security mechanism by combining a delay testable circuit based on boundary scan design and a PUF (physically
unclonable function) circuit. We have already confirmed that the unique values generated by the proposed circuit can be utilized as a PUF. However, it is not evaluated whether the proposed circuit can be available as a PUF under temperature variations. In this paper, we investigate the prototype IC under varying temperatures and evaluate the generated unique values for evaluating PUF performance. The results show that the proposed circuit has both high uniqueness and stability. We also confirmed the generated unique values can achieve the individual identification of
chips.
Keyword (in Japanese) (See Japanese page) 
(in English) PUF / delay tesing using design-for-testability / unanimous selection method / individual identification / temperature variation / / /  
Reference Info. IEICE Tech. Rep., vol. 122, no. 285, DC2022-62, pp. 156-161, Nov. 2022.
Paper # DC2022-62 
Date of Issue 2022-11-21 (VLD, ICD, DC, RECONF) 
ISSN Online edition: ISSN 2432-6380
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Download PDF VLD2022-46 ICD2022-63 DC2022-62 RECONF2022-69

Conference Information
Committee VLD DC RECONF ICD IPSJ-SLDM  
Conference Date 2022-11-28 - 2022-11-30 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2022 -New Field of VLSI Design- 
Paper Information
Registration To DC 
Conference Code 2022-11-VLD-DC-RECONF-ICD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On the performance evaluation of a PUF circuit using the Delay Testable Circuit under temperature effects 
Sub Title (in English)  
Keyword(1) PUF  
Keyword(2) delay tesing using design-for-testability  
Keyword(3) unanimous selection method  
Keyword(4) individual identification  
Keyword(5) temperature variation  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Eisuke Ohama  
1st Author's Affiliation Tokushima University (Tokushima Univ.)
2nd Author's Name Hiroyuki Yotsuyanagi  
2nd Author's Affiliation Tokushima University (Tokushima Univ.)
3rd Author's Name Masaki Hashizume  
3rd Author's Affiliation Tokushima University (Tokushima Univ.)
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Speaker Author-1 
Date Time 2022-11-30 14:20:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # VLD2022-46, ICD2022-63, DC2022-62, RECONF2022-69 
Volume (vol) vol.122 
Number (no) no.283(VLD), no.284(ICD), no.285(DC), no.286(RECONF) 
Page pp.156-161 
#Pages
Date of Issue 2022-11-21 (VLD, ICD, DC, RECONF) 


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