IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2022-12-08 14:00
[Poster Presentation] Mapping to Nearest-Neighbor Architectures by Appling Gaussian Elimination Iteratively
Zanhe Qi, Shigeru Yamashita (Ritsumeikan Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) Quantum circuits should be implemented on a so-called Nearest Neighbor Architecture (NNA) that supports two-qubit operations only between adjacent two qubits. Thus, we usually convert a quantum circuit to an NNA-compliant circuit by inserting SWAP gates. Without inserting SWAP gates, we can usually generate a smaller NNA-compliant quantum circuit consisting of CNOT gates by utilizing Gaussian Elimination. This paper reveals that we can improve the Gaussian Elimination-based method by inserting CNOT gates before and/or after the target circuit in many cases. This paper shows that we can reduce the number of CNOT gates by about 15% compared to the original Gaussian Elimination-based method by inserting CNOT gates into initial circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) earest Neighbor Architecture (NNA)-compliant / Gaussian Elimination / Inserting CNOT gates / / / / /  
Reference Info. IEICE Tech. Rep.
Paper #  
Date of Issue  
ISSN  
Download PDF

Conference Information
Committee QIT  
Conference Date 2022-12-08 - 2022-12-09 
Place (in Japanese) (See Japanese page) 
Place (in English) Keio Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Quantum Information 
Paper Information
Registration To QIT 
Conference Code 2022-12-QIT 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Mapping to Nearest-Neighbor Architectures by Appling Gaussian Elimination Iteratively 
Sub Title (in English)  
Keyword(1) earest Neighbor Architecture (NNA)-compliant  
Keyword(2) Gaussian Elimination  
Keyword(3) Inserting CNOT gates  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Zanhe Qi  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Shigeru Yamashita  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
3rd Author's Name  
3rd Author's Affiliation ()
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2022-12-08 14:00:00 
Presentation Time 60 minutes 
Registration for QIT 
Paper #  
Volume (vol) vol. 
Number (no)  
Page  
#Pages  
Date of Issue  


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan