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| Presentation | 2023-01-23 10:30 Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ)  VLD2022-56 RECONF2022-79 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Multi-FPGA systems, in which multiple FPGA boards are directly connected via high-speed serial links, are attracting attention as compute nodes for MEC (Multi-edgeaccess Computing), but development on multi-FPGA systems requires human intervention to partition applications. However, the development of multi-FPGA systems requires human intervention for application partitioning.Even after partitioning, a table for setting communication paths between boards must be manually created, and if the communication paths change depending on the board used, it is necessary to change the table each time. In this paper, we have improved the flow of the multi-FPGA board design environment for the MKUBOS cluster by dividing applications and automatically generating communication path setting tables to be used during implementation using the high-level synthesis tools CyberWorkbench (CWB) and SystemC. The flow of the multi-FPGA board design environment was improved.The LeNet program was implemented, and the evaluation was 78.890[ms] when splitting manually and 78.892[ms] when using the improved design flow, showing that the performance did not drop compared to manual splitting and that the use of the design flow saved time and effort. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Multi-FPGA Systems / Dynamic partial reconfiguration / / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 122, no. 354, RECONF2022-79, pp. 1-6, Jan. 2023. | |
| Paper # | RECONF2022-79 | |
| Date of Issue | 2023-01-16 (VLD, RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2022-56 RECONF2022-79 |
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| Conference Information | |
| Committee | IPSJ-SLDM RECONF VLD |
| Conference Date | 2023-01-23 - 2023-01-24 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Raiosha, Hiyoshi Campus, Keio University |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | FPGA Applications, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2023-01-SLDM-RECONF-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool |
| Sub Title (in English) | |
| Keyword(1) | Multi-FPGA Systems |
| Keyword(2) | Dynamic partial reconfiguration |
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| 1st Author's Name | Hiroaki Suzuki |
| 1st Author's Affiliation | Keio University (Keio Univ) |
| 2nd Author's Name | Wataru Takahashi |
| 2nd Author's Affiliation | NEC Corporation (NEC) |
| 3rd Author's Name | Kazutoshi Wakabayashi |
| 3rd Author's Affiliation | The University of Tokyo (Tokyo Univ) |
| 4th Author's Name | Hideharu Amano |
| 4th Author's Affiliation | Keio University (Keio Univ) |
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| Speaker | Author-1 |
| Date Time | 2023-01-23 10:30:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | VLD2022-56, RECONF2022-79 |
| Volume (vol) | vol.122 |
| Number (no) | no.353(VLD), no.354(RECONF) |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2023-01-16 (VLD, RECONF) |
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