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Paper Abstract and Keywords
Presentation 2023-01-24 13:30
Implementing a quantum computer simulator Qulacs on FPGAs
Hideharu Amano, Wei Kaijie (Keio Univ.), Takefumi Miyoshi (Wasalab.), Yoshiki Yamaguchi, Ryohei Niwase (U.niv. of Tsukuba) VLD2022-72 RECONF2022-95
Abstract (in Japanese) (See Japanese page) 
(in English) Quantum computer simulation is indispensable for quantum algorithm research since the results of real
quantum computers are influenced by noise and inaccurate controls. Although state vector simulations can show all
states of qubits during computation, they require 2n+4B memory to store all states. Thus, the simulation with more
than 30 qubits is challenging to be executed. This paper proposes to use a Trefoil FPGA board with an extensive
storage system for the quantum simulation. Since Trefoil is not available now, we implemented a high-speed quantum
simulator Qulacs, on M-KUBOS FPGA cluster. The performance of H gate, S gate, CNOT gate, and a dense matrix
computation for 28-qubit was approximately 1/4 of that of the Ryzen server. By introducing buffering and parallel
computation techniques, the performance was improved to a similar level to that of the server. The simulation with
29-qubit is almost the same execution time as 28-qubit when two boards are used in parallel.
Keyword (in Japanese) (See Japanese page) 
(in English) Quantum computer simulation / Multi-FPGA systems / State vector method / / / / /  
Reference Info. IEICE Tech. Rep., vol. 122, no. 354, RECONF2022-95, pp. 74-79, Jan. 2023.
Paper # RECONF2022-95 
Date of Issue 2023-01-16 (VLD, RECONF) 
ISSN Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee IPSJ-SLDM RECONF VLD  
Conference Date 2023-01-23 - 2023-01-24 
Place (in Japanese) (See Japanese page) 
Place (in English) Raiosha, Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc. 
Paper Information
Registration To RECONF 
Conference Code 2023-01-SLDM-RECONF-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Implementing a quantum computer simulator Qulacs on FPGAs 
Sub Title (in English)  
Keyword(1) Quantum computer simulation  
Keyword(2) Multi-FPGA systems  
Keyword(3) State vector method  
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1st Author's Name Hideharu Amano  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Wei Kaijie  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Takefumi Miyoshi  
3rd Author's Affiliation Wasalabo (Wasalab.)
4th Author's Name Yoshiki Yamaguchi  
4th Author's Affiliation University of Tsukuba (U.niv. of Tsukuba)
5th Author's Name Ryohei Niwase  
5th Author's Affiliation University of Tsukuba (U.niv. of Tsukuba)
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Speaker Author-1 
Date Time 2023-01-24 13:30:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # VLD2022-72, RECONF2022-95 
Volume (vol) vol.122 
Number (no) no.353(VLD), no.354(RECONF) 
Page pp.74-79 
#Pages
Date of Issue 2023-01-16 (VLD, RECONF) 


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