講演抄録/キーワード |
講演名 |
2023-03-02 13:25
[記念講演]Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects ○Takuma Nagao(NAIST)・Tomoki Nakamura・Masuo Kajiyama・Makoto Eiki(Sony Semiconductor Manufacturing)・Michiko Inoue(NAIST)・Michihiro Shintani(Kyoto Institute of Technology) VLD2022-91 HWS2022-62 |
抄録 |
(和) |
(まだ登録されていません) |
(英) |
Statistical wafer-level variation modeling is an attractive method for reducing the measurement cost in large-scale integrated circuit (LSI) testing while maintaining the test quality. In this method, the performance of unmeasured LSI circuits manufactured on a wafer is statistically predicted from a few measured LSI circuits. Conventional statistical methods model spatially smooth variations in wafer. However, actual wafers may have discontinuous variations that are systematically caused by the manufacturing environments, such as shot dependence. In this study, we propose a modeling method that considers discontinuous variations in wafer characteristics by applying the knowledge of manufacturing engineers to a model estimated using Gaussian process regression. In the proposed method, the process variation is decomposed into the systematic discontinuous and global components to improve the estimation accuracy. An evaluation performed using an industrial production test dataset shows that the proposed method reduces the estimation error for an entire wafer by over 33% compared to conventional
methods. |
キーワード |
(和) |
Wafer-level spatial characteristic modeling / Process variation / Gaussian process regression / / / / / |
(英) |
/ / / / / / / |
文献情報 |
信学技報, vol. 122, no. 402, VLD2022-91, pp. 109-109, 2023年3月. |
資料番号 |
VLD2022-91 |
発行日 |
2023-02-22 (VLD, HWS) |
ISSN |
Online edition: ISSN 2432-6380 |
著作権に ついて |
技術研究報告に掲載された論文の著作権は電子情報通信学会に帰属します.(許諾番号:10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
PDFダウンロード |
VLD2022-91 HWS2022-62 |
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