Paper Abstract and Keywords |
Presentation |
2023-03-03 13:50
A Logic Locking Method based on Function Modification Circuit Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Rei Miura, Toshinori Hosokawa (Nihon Univ.) VLD2022-107 HWS2022-78 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In recent years, with the increase of VLSI integration, semiconductor design companies to design a VLSI have tended to use IP core and to be fabless companies to reduce costs. However, an unreliable VLSI manufacturing company can manufacture a VLSI outside the contract. Therefore, infringement of IP core copyrights has become a problem. Logic Locking has been proposed for protecting the copyrights of the IP core. SAT and FALL attacks have been reported to invalidate existing logic-locking methods. This paper proposes a logic Locking method based on a function modification circuit resistant to SAT and FALL attacks. Experiments show that the proposed logic locking method resists SAT and FALL attacks. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Logic Locking / SAT attack / FALL attack / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 122, no. 402, VLD2022-107, pp. 185-190, March 2023. |
Paper # |
VLD2022-107 |
Date of Issue |
2023-02-22 (VLD, HWS) |
ISSN |
Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2022-107 HWS2022-78 |
Conference Information |
Committee |
HWS VLD |
Conference Date |
2023-03-01 - 2023-03-04 |
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(See Japanese page) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2023-03-HWS-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Logic Locking Method based on Function Modification Circuit |
Sub Title (in English) |
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Logic Locking |
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SAT attack |
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FALL attack |
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1st Author's Name |
Yohei Noguchi |
1st Author's Affiliation |
Kyoto Sangyo University (Kyoto Sangyo Univ.) |
2nd Author's Name |
Masayoshi Yoshimura |
2nd Author's Affiliation |
Kyoto Sangyo University (Kyoto Sangyo Univ.) |
3rd Author's Name |
Rei Miura |
3rd Author's Affiliation |
Nihon University (Nihon Univ.) |
4th Author's Name |
Toshinori Hosokawa |
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Nihon University (Nihon Univ.) |
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Speaker |
Author-1 |
Date Time |
2023-03-03 13:50:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2022-107, HWS2022-78 |
Volume (vol) |
vol.122 |
Number (no) |
no.402(VLD), no.403(HWS) |
Page |
pp.185-190 |
#Pages |
6 |
Date of Issue |
2023-02-22 (VLD, HWS) |
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