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| Presentation | 2023-06-08 16:00 Parallelization of Prim's Algorithm Using FPGA and Its Performance Evaluation Noritsune O, Kenji Kanazawa, Moritoshi Yasunaga (Univ. of Tsukuba)  RECONF2023-3 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A subgraph of an undirected graph G that is connected and contains no closed paths is called a tree, a global tree is a tree that contains all vertices of G, and a minimum global tree is a global tree with the minimum total cost of all its branches. There are many applications of minimum global tree, such as optimal design of communication networks and calculation of upper and lower bounds in traveling salesman problems. In this study, we implemented the Prim's method, one of the exact solution methods for minimum global tree, in parallel on FPGA and evaluated its performance. The evaluation results showed that the proposed method was the fastest, 2.1 times faster than the execution speed on Intel CPUs. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / Prim's algorithm / High-Level Synthesis / Parallelization / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 123, no. 71, RECONF2023-3, pp. 13-16, June 2023. | |
| Paper # | RECONF2023-3 | |
| Date of Issue | 2023-06-01 (RECONF) | |
| ISSN | Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Notes on Review | This article is a technical report without peer review, and its polished version will be published elsewhere. | |
| Download PDF | RECONF2023-3 |
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| Conference Information | |
| Committee | RECONF |
| Conference Date | 2023-06-08 - 2023-06-09 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Eikokuji Campus, Kochi University of Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Reconfigurable system, etc. |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2023-06-RECONF |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Parallelization of Prim's Algorithm Using FPGA and Its Performance Evaluation |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Prim's algorithm |
| Keyword(3) | High-Level Synthesis |
| Keyword(4) | Parallelization |
| Keyword(5) | |
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| Keyword(8) | |
| 1st Author's Name | Noritsune O |
| 1st Author's Affiliation | University of Tsukuba (Univ. of Tsukuba) |
| 2nd Author's Name | Kenji Kanazawa |
| 2nd Author's Affiliation | University of Tsukuba (Univ. of Tsukuba) |
| 3rd Author's Name | Moritoshi Yasunaga |
| 3rd Author's Affiliation | University of Tsukuba (Univ. of Tsukuba) |
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| Speaker | Author-1 |
| Date Time | 2023-06-08 16:00:00 |
| Presentation Time | 25 minutes |
| Registration for | RECONF |
| Paper # | RECONF2023-3 |
| Volume (vol) | vol.123 |
| Number (no) | no.71 |
| Page | pp.13-16 |
| #Pages | 4 |
| Date of Issue | 2023-06-01 (RECONF) |
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