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Paper Abstract and Keywords
Presentation 2023-10-31 15:00
Side-Channel Leakage Evaluation of 3D CMOS Chip Stacking
Kazuki Monta, Rikuu Hasegawa, Takuji Miki, Makoto Nagata (Kobe Univ.) HWS2023-57 ICD2023-36
Abstract (in Japanese) (See Japanese page) 
(in English) 2.5D and 3D packaging are methodologies that include multiple integrated circuit (IC) chips. They deliver enhanced performance, lower latency and power performance. Cryptography hardware modules are vulnerable to side-channel (SC) attacks. In this paper, we focus on the security level of multi-chip modules. Electromagnetic (EM) noise from multi-chip module demonstrators with crypto module is captured and evaluated for SC leakage. And also, we introduce an SC leakage mitigation methodology applicable for 3D integrated circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) Cryptographic module / Electromagnetic (EM) noise / Side channel leakage / 3D CMOS chip stacks / Si substrate backside / Power supply noise / /  
Reference Info. IEICE Tech. Rep., vol. 123, no. 235, HWS2023-57, pp. 16-19, Oct. 2023.
Paper # HWS2023-57 
Date of Issue 2023-10-24 (HWS, ICD) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF HWS2023-57 ICD2023-36

Conference Information
Committee ICD HWS  
Conference Date 2023-10-31 - 2023-10-31 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Hardware Security, etc. 
Paper Information
Registration To HWS 
Conference Code 2023-10-ICD-HWS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Side-Channel Leakage Evaluation of 3D CMOS Chip Stacking 
Sub Title (in English)  
Keyword(1) Cryptographic module  
Keyword(2) Electromagnetic (EM) noise  
Keyword(3) Side channel leakage  
Keyword(4) 3D CMOS chip stacks  
Keyword(5) Si substrate backside  
Keyword(6) Power supply noise  
Keyword(7)  
Keyword(8)  
1st Author's Name Kazuki Monta  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Rikuu Hasegawa  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Takuji Miki  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Makoto Nagata  
4th Author's Affiliation Kobe University (Kobe Univ.)
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Speaker Author-1 
Date Time 2023-10-31 15:00:00 
Presentation Time 25 minutes 
Registration for HWS 
Paper # HWS2023-57, ICD2023-36 
Volume (vol) vol.123 
Number (no) no.235(HWS), no.236(ICD) 
Page pp.16-19 
#Pages
Date of Issue 2023-10-24 (HWS, ICD) 


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