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Paper Abstract and Keywords
Presentation 2023-12-07 11:00
Data Path Parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware
Yuka Otani, Akira Yamawaki (Kyutech) SIS2023-24
Abstract (in Japanese) (See Japanese page) 
(in English) A mobile terminal architecture which can dynamically reconfigure the optimal hardware for each application can achieve higher performance and lower power consumption compared with a conventional one. We are developing a software game library so that the high-level synthesis, HLS, can automatically generate an efficient hardware module in such mobile terminals. The HLS library must be built with deep consideration of hardware organization. Otherwise, the HLS converts software into a large and slow hardware module. This paper focuses on the drawing of 2D sprite characters. Character movement is achieved by repeatedly compositing the background image and sprite image during drawing. The data paths are parallelized on the sprite drawing process so that the HLS can produce better hardware. The experiments confirm the effectiveness of the proposed method on the actual machine and simulation.
Keyword (in Japanese) (See Japanese page) 
(in English) High-Level Synthesis (HLS) / Sprite / Drawing / Game library / Parallel / FPGA / Low-power / High-performance  
Reference Info. IEICE Tech. Rep., vol. 123, no. 296, SIS2023-24, pp. 1-6, Dec. 2023.
Paper # SIS2023-24 
Date of Issue 2023-11-30 (SIS) 
ISSN Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SIS2023-24

Conference Information
Committee SIS  
Conference Date 2023-12-07 - 2023-12-08 
Place (in Japanese) (See Japanese page) 
Place (in English) Sakurayama Campus, Nagoya City University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Smart Personal Sysytems, etc. 
Paper Information
Registration To SIS 
Conference Code 2023-12-SIS 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Data Path Parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware 
Sub Title (in English)  
Keyword(1) High-Level Synthesis (HLS)  
Keyword(2) Sprite  
Keyword(3) Drawing  
Keyword(4) Game library  
Keyword(5) Parallel  
Keyword(6) FPGA  
Keyword(7) Low-power  
Keyword(8) High-performance  
1st Author's Name Yuka Otani  
1st Author's Affiliation Kyushu Institute of Technology (Kyutech)
2nd Author's Name Akira Yamawaki  
2nd Author's Affiliation Kyushu Institute of Technology (Kyutech)
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Speaker Author-1 
Date Time 2023-12-07 11:00:00 
Presentation Time 20 minutes 
Registration for SIS 
Paper # SIS2023-24 
Volume (vol) vol.123 
Number (no) no.296 
Page pp.1-6 
#Pages 6 
Date of Issue 2023-11-30 (SIS) 

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