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Presentation
[Invited Talk] Circuit Failure Prediction by Field Test (DART) with Delay-Shift Measurement Mechanism
Yasuo Sato, Seiji Kajihara (Kyusyu Institute of Technology), Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara (NAIST), Yukiya Miura (Tokyo Metropolitan Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) The main task of test had traditionally been screening of hard defects before shipping. However, current chips are taking risk of field reliability with rapidly reducing marginality due to increasing process variations and degradation mechanisms (e.g. NBTI, HCI, TDDB), which are difficult to detect in fabrication test. Therefore, effective methodologies that guarantee quality in the field are strongly required. This paper presents a novel testing mechanism for high field reliability. An on-line testing in intervals at a power-on/off time of a system or at system’s vacant time detects the circuits’ delay degradation and confirms its marginality. The proposed testing technology will predict a circuit failure caused by degradation, and the system will be able to avoid sudden failure, which would have caused a catastrophic damage in field. We firstly survey the related works, then, discuss the required features that differentiate field testing from traditional production testing, and finally, introduce the proposed methodology.
Keyword (in Japanese) (See Japanese page) 
(in English) Degradation / Field Test / Delay Measurement / DFT / BIST / Ring Oscillator / NBTI / Power-On Test  
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Conference Information
Committee ICD  
Conference Date 2010-08-16 - 2010-08-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Ho Chi Minh City University of Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Integrated Circuits and Devices in Vietnam 2010 
Paper Information
Registration To ICD 
Conference Code 2010-08-ICD 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Circuit Failure Prediction by Field Test (DART) with Delay-Shift Measurement Mechanism 
Sub Title (in English)  
Keyword(1) Degradation  
Keyword(2) Field Test  
Keyword(3) Delay Measurement  
Keyword(4) DFT  
Keyword(5) BIST  
Keyword(6) Ring Oscillator  
Keyword(7) NBTI  
Keyword(8) Power-On Test  
1st Author's Name Yasuo Sato  
1st Author's Affiliation Kyusyu Institute of Technology (Kyusyu Institute of Technology)
2nd Author's Name Seiji Kajihara  
2nd Author's Affiliation Kyusyu Institute of Technology (Kyusyu Institute of Technology)
3rd Author's Name Michiko Inoue  
3rd Author's Affiliation Nara Institute of Science and Technology (NAIST)
4th Author's Name Tomokazu Yoneda  
4th Author's Affiliation Nara Institute of Science and Technology (NAIST)
5th Author's Name Satoshi Ohtake  
5th Author's Affiliation Nara Institute of Science and Technology (NAIST)
6th Author's Name Hideo Fujiwara  
6th Author's Affiliation Nara Institute of Science and Technology (NAIST)
7th Author's Name Yukiya Miura  
7th Author's Affiliation Tokyo Metropolitan University (Tokyo Metropolitan Univ.)
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