Paper Abstract and Keywords |
Presentation |
[Invited Talk]
Circuit Failure Prediction by Field Test (DART) with Delay-Shift Measurement Mechanism Yasuo Sato, Seiji Kajihara (Kyusyu Institute of Technology), Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara (NAIST), Yukiya Miura (Tokyo Metropolitan Univ.) |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The main task of test had traditionally been screening of hard defects before shipping. However, current chips are taking risk of field reliability with rapidly reducing marginality due to increasing process variations and degradation mechanisms (e.g. NBTI, HCI, TDDB), which are difficult to detect in fabrication test. Therefore, effective methodologies that guarantee quality in the field are strongly required. This paper presents a novel testing mechanism for high field reliability. An on-line testing in intervals at a power-on/off time of a system or at system’s vacant time detects the circuits’ delay degradation and confirms its marginality. The proposed testing technology will predict a circuit failure caused by degradation, and the system will be able to avoid sudden failure, which would have caused a catastrophic damage in field. We firstly survey the related works, then, discuss the required features that differentiate field testing from traditional production testing, and finally, introduce the proposed methodology. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Degradation / Field Test / Delay Measurement / DFT / BIST / Ring Oscillator / NBTI / Power-On Test |
Reference Info. |
IEICE Tech. Rep. |
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