Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) |
[schedule] [select]
|
|
Chair |
|
Kazutoshi Wakabayashi |
Secretary |
|
Naohito Kojima, Hiroaki Komatsu, Nozomu Togawa |
|
|
Chair |
|
Akira Onozawa (NTT) |
Vice Chair |
|
Kimiyoshi Usami (Shibaura Inst. of Tech.) |
Secretary |
|
Akihisa Yamada (Sharp), Kazutoshi Kobayashi (Kyoto Inst. of Tech.) |
|
Conference Date |
Wed, May 18, 2011 14:15 - 17:50
Thu, May 19, 2011 09:30 - 14:35 |
Topics |
System Design, etc. |
Conference Place |
Kitakyushu International Conference Center |
Transportation Guide |
http://www.convention-a.jp/access/ |
Contact Person |
Prof. Yasuhiro Takashima
+81-93-695-3729 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Wed, May 18 PM 14:15 - 15:30 |
(1) VLD |
14:15-14:40 |
Study of the slew-rate contorol system for reducing far-end crosstalk VLD2011-1 |
Kazunori Nakashima, Suguru Kato, Shinichi Sasaki (Saga Univ) |
(2) VLD |
14:40-15:05 |
An Effective Overlap Removable Objective for Analytical Placement VLD2011-2 |
Syota Kuwabara, Yukihide Kohira (Univ. of Aizu), Yasuhiro Takashima (Univ. of Kitakyushu) |
(3) VLD |
15:05-15:30 |
Path Encoding Method for High Speed Frequency-Mapping Associative Memory VLD2011-3 |
Seiryu Sasaki, Masahiro Yasuda, Akio Kawabata, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.) |
|
15:30-15:45 |
Break ( 15 min. ) |
Wed, May 18 PM 15:45 - 16:45 |
(4) VLD |
15:45-16:45 |
[Invited Talk]
Recent Gating-Techniques for Power Reduction VLD2011-4 |
Kimiyoshi Usami (Shibaura Inst. of Tech.) |
|
16:45-16:50 |
Break ( 5 min. ) |
Wed, May 18 PM 16:50 - 17:50 |
(5) VLD |
16:50-17:50 |
[Invited Talk]
Low Power Design Technology on Algorithm/Architecture Level for Video Processing VLD2011-5 |
Satoshi Goto (Waseda Univ.) |
Thu, May 19 AM 09:30 - 10:45 |
(6) VLD |
09:30-09:55 |
Super-resolution by UsingWeighted Adders with Selector Logics VLD2011-6 |
Hiromine Yoshihara, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) |
(7) VLD |
09:55-10:20 |
Multi-Stage Power Gating Based on Controlling Values of Logic Gates VLD2011-7 |
Jin Yu, Shinji Kimura (Waseda Univ.) |
(8) |
10:20-10:45 |
|
|
10:45-10:55 |
Break ( 10 min. ) |
Thu, May 19 AM 10:55 - 12:10 |
(9) |
10:55-11:20 |
|
(10) |
11:20-11:45 |
|
(11) |
11:45-12:10 |
|
|
12:10-13:20 |
Lunch Break ( 70 min. ) |
Thu, May 19 PM 13:20 - 14:35 |
(12) |
13:20-13:45 |
|
(13) |
13:45-14:10 |
|
(14) |
14:10-14:35 |
|
Announcement for Speakers |
General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
Contact Address and Latest Schedule Information |
IPSJ-SLDM |
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
|
Contact Address |
|
VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
Contact Address |
Akihisa Yamada (Sharp)
E-: asrp
Tel: +81-743-65-2531, Fax: +81-743-65-0554 |
Announcement |
See also VLD's homepage:
http://www.ieice.org/~vld/ |
Last modified: 2011-05-16 11:31:06
|