Mon, Feb 16 AM 10:00 - 11:15 |
(1) |
10:00-10:25 |
On the Acceleration of Threshold Test Generation Based on Fault Acceptability |
Yusuke Nakashima, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ) |
(2) |
10:25-10:50 |
A test pattern generation method to reduce the number of detected untestable faults on scan testing |
Masayoshi Yoshimura (Kyusyu Univ.), Hiroshi Ogawa (Nihon Univ.), Yusyo Omori (Fujitsu Microelectronics), Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meizi Univ.) |
(3) |
10:50-11:15 |
On the Acceleration of Redundancy Identification for Hard-to-ATPG faults Using SAT |
Yusuke Akiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.) |
|
11:15-11:30 |
Break ( 15 min. ) |
Mon, Feb 16 AM 11:30 - 12:20 |
(4) |
11:30-11:55 |
Decimal adder using abacus architecture and its application to residue arithmetic |
Tadahito Iijima, Shugang Wei (Gunma Univ.) |
(5) |
11:55-12:20 |
History based scheduling for reliable Volunteer Computing |
Ryo Fujita, Kan Watanabe, Masaru Fukushi, Susumu Horiguchi (GSIS, Tohoku Univ.) |
|
12:20-13:50 |
Lunch Break ( 90 min. ) |
Mon, Feb 16 PM 13:50 - 15:05 |
(6) |
13:50-14:15 |
A method for generating defect oriented test patterns for combinational circuits |
Hiroshi Takahashi, Yoshinobu Higami, Taisuke Izumi, Takashi Aikyo, Yuzo Takamatsu (Ehime Univ.) |
(7) |
14:15-14:40 |
On Tests to Detect Open faults with Considering Adjacent Lines |
Tetsuya Watanabe, Hiroshi Takahashi, Yoshinobu Higami (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ, Tokushima), Yuzo Takamatsu (Ehime Univ.) |
(8) |
14:40-15:05 |
Note on Small Delay Fault Model for Intra-Gate Resistive Open Defects |
Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki (Tokyo Metro. Univ.), Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo (STARC) |
|
15:05-15:20 |
Break ( 15 min. ) |
Mon, Feb 16 PM 15:20 - 16:35 |
(9) |
15:20-15:45 |
A Method to Increase the Number of Don't care based on Easy- To-Detected Faults
-- Application for BAST Architecture -- |
LingLing Wan (Graduate Schoo of Nihon Univ.), Motohiro Wakazono (Graduate School of Nihon Univ.), Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) |
(10) |
15:45-16:10 |
Resource Binding to Minimize the Number of RTL Paths |
Yuichi Uemoto, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Scie and Tech.) |
(11) |
16:10-16:35 |
A Secure Scan Design Approach using Extended de Bruijn Graph |
Hideo Fujiwara, Marie Engelene J. Obien (NAIST) |