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09:50-10:00 |
Opening Address ( 10 min. ) |
Wed, Mar 3 AM VLD-1:Deep Learning 10:00 - 11:40 |
(1) |
10:00-10:25 |
Energy Efficient Approximate Storing to MRAM for Deep Neural Network Tasks in Edge Computing |
Yoshinori Ono, Kimiyoshi Usami (SIT) |
(2) |
10:25-10:50 |
Evaluation on Approximate Multiplier for CNN Calculation |
Yuechuan Zhang, Masahiro Fujita, Takashi Matsumoto (UTokyo) |
(3) |
10:50-11:15 |
A performance and resources estimation of AI Inference circuit on FPGAs |
Ryo Yamamoto, Iwagawa Hidetoshi, Yoshihiro Ogawa (MELCO) |
(4) |
11:15-11:40 |
The Design and Development of of Quantized Neural Networks Library for Exact Hardware Emulation |
Masato Kiyama, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.) |
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11:40-13:00 |
Lunch Break ( 80 min. ) |
Wed, Mar 3 PM VLD:Commemorative Lecture 13:00 - 14:15 |
(5) |
13:00-13:25 |
[Memorial Lecture]
Scheduling Sparse Matrix-Vector Multiplication onto Parallel Communication Architecture |
Mingfei Yu, Ruitao Gao, Masahiro Fujita (Univ. Tokyo) |
(6) |
13:25-13:50 |
[Memorial Lecture]
Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization |
TaiYu Cheng (Osaka Univ.), Yutaka Masuda (Nagoya Univ.), Jun Nagayama, Yoichi Momiyama (Socionext Inc.), Jun Chen, Masanori Hashimoto (Osaka Univ.) |
(7) |
13:50-14:15 |
[Memorial Lecture]
Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures |
Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita (Ritsumeikan University) |
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14:15-14:30 |
Break ( 15 min. ) |
Wed, Mar 3 PM VLD-2:Algorithm and Circuit System 14:30 - 15:45 |
(8) |
14:30-14:55 |
Measurement of Voltage-variation-tolerant Temperature Sensor for Standard CMOS Chip with On-chip Solar Cell |
Shuto Murohara, Tatsuya Banno, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) |
(9) |
14:55-15:20 |
Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems |
Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) |
(10) |
15:20-15:45 |
Heuristic Algorithms for Dynamic Scheduling of Moldable Tasks in Multicore Embedded Systems |
Takuma Hikida, Hiroki Nishikawa, Hiroyuki Tomiyama (Ritsumeikan Univ.) |
|
15:45-16:00 |
Break ( 15 min. ) |
Wed, Mar 3 PM Hardware Trojan・Security Chip 16:00 - 16:50 |
(11) |
16:00-16:25 |
Highly Efficient Simulation Method to Find Hardware Trojans Hidden in Semiconductor Chips |
Kazuki Yasuda, Kazuki Monta, Daichi Nakagawa, Masaru Mashiba, Takuji Miki, Makoto Nagata (Kobe Univ.) |
(12) |
16:25-16:50 |
Counteracting Chip Transplantation Attack using Hologram on Epoxy Covering |
Takashi Sudo, Takeshi Sugawara (UEC) |
Thu, Mar 4 AM VLD-3:Design Technology 09:30 - 10:45 |
(13) |
09:30-09:55 |
Design space exploration on low energy embedded multi-core processors |
Sayuri Onagi, Yuko Hara (Tokyo Tech) |
(14) |
09:55-10:20 |
High-level synthesis of approximate circuits with two-level accuracies |
Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritumeikan Univ.) |
(15) |
10:20-10:45 |
A Fundamental Study on Three-Dimensional Module Placement for Layered Three-Dimensional LSI |
Tomohiro Noguchi, Hindawi Omran, Mineo Kaneko (JAIST) |
Thu, Mar 4 AM VLD:Special Lecture 10:45 - 11:45 |
(16) |
10:45-11:45 |
[Special Talk]
Efficient VLSI Layout Data Structures and Algorithms
-- a Brief Tutorial -- |
Shmuel Wimer (Bar-Ilan University) |
|
11:45-13:00 |
Lunch Break ( 75 min. ) |
Thu, Mar 4 PM HWS-2:Design of Hardware 13:00 - 14:40 |
(17) |
13:00-13:25 |
Design of Area-Efficient Response Generator for CMOS Image Sensor PUF |
Masanori Aoki, Shunsuke Okura, Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.) |
(18) |
13:25-13:50 |
A Low-Latency Memory Encryption Scheme with Tweakable Block Cipher and Its Hardware Design |
Maya Oda, Rei Ueno, Naofumi Homma (Tohoku Univ.), Akiko Inoue, Kazuhiko Minematsu (NEC) |
(19) |
13:50-14:15 |
Design and Evaluation of Efficient AES S-box Hardware with Optimization of Linear Mappings |
Ayano Nakashima, Rei Ueno, Naofumi Homma (Tohoku Univ.) |
(20) |
14:15-14:40 |
Experiments of Data Authenticity Verification in Multi-Node IoT Systems Using Elliptic Curve Digital Signature Chips |
Yuya Takahashi, Takuya Matsumaru, Kazuki Monta (Kobe Univ.), Toshihiro Sato, Takaaki Okidono (ECSEC Lab), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.) |
|
14:40-14:55 |
Break ( 15 min. ) |
Thu, Mar 4 PM HWS-3:Side-Channel Attacks 14:55 - 15:45 |
(21) |
14:55-15:20 |
FPGA Implementation of Lightweight Cipher Chaskey through High-Level Synthesis and its Evaluation of Side-Channel Attack Resistance |
Saya Inagaki, Mingyu Yang (Tokyo Tech), Yang Li, Kazuo Sakiyama (UEC), Yuko Hara (Tokyo Tech) |
(22) |
15:20-15:45 |
Power Analysis Attack on a Unrolled Midori128 and its Evaluation |
Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) |
|
15:45-16:00 |
Break ( 15 min. ) |
Thu, Mar 4 PM HWS-4:System Security 16:00 - 17:40 |
(23) |
16:00-16:25 |
Survey on intrusion detection system for Vehicle Security Techniques |
Ayaka Matsushita, Takao Okubo (IISEC) |
(24) |
16:25-16:50 |
Security Evaluation of an IoT Cloud Service against Local Attacks |
Makoto Ishida, Takeshi Sugawara (UEC) |
(25) |
16:50-17:15 |
Screen Information Reconstruction from High Resolution Displays Focusing on Multiple Leakage Frequencies |
Kimihiro Arai, Daisuke Fujimoto, Yuichi Hayashi (NAIST) |
(26) |
17:15-17:40 |
Fundamental Study on Evaluation of EM Information Leakage from Smart Speakers with Different Installation Environments and Its Countermeasures |
Shogo Fukushima, Daisuke Fujimoto, Yuichi Hayashi (NAIST) |