IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   Prev CAS Conf / Next CAS Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on Circuits and Systems (CAS) [schedule] [select]
Chair Hisanori Fujisawa (Fujitsu Labs.)
Vice Chair Mitsunori Makino (Chuo Univ.)
Secretary Hiroshi Yamazaki (Fujitsu Labs.), Taketomo Kanazawa (Shibaura Inst. of Tech.)
Assistant Daisuke Takafuji (Hiroshima Univ.)

Technical Committee on Concurrent Systems Technology (CST)
Chair Toshimitsu Ushio (Osaka Univ.)
Vice Chair Kunihiko Hiraishi (JAIST)
Secretary Shingo yamaguchi (Yamaguchi Univ.), Masaki Nakamura (Kanazawa Univ.)
Assistant Tatsushi Yamasaki (Setsunan Univ.)

Conference Date Thu, Nov 26, 2009 10:45 - 16:50
Fri, Nov 27, 2009 09:30 - 17:30
Topics  
Conference Place Venture Business Laboratory, Nagoya University 
Transportation Guide http://www.vbl.nagoya-u.ac.jp/access/index.html
Contact
Person
Dr. Mutsunori Yagiura

Thu, Nov 26 AM  CST(1)
10:45 - 12:00
(1) 10:45-11:10 On a new model for Quantum Computers by using Quantum Petri Nets Shinsuke Ito, Atsushi Ohta, Kohkichi Tsuji (Aichi Pref. Univ.)
(2) 11:10-11:35 Extending the Legal Firing Sequence Problem of Petri Nets and Making a General-Purpose Scheduler for Web-Based Applications Masanori Nakano, Masahiro Yamauchi (Kinki Univ.), Satoshi Taoka, Toshimasa Watanabe (Hiroshima Univ.)
(3) 11:35-12:00 Advanced Technologies for Dependable Systems through Product Lifecycle by Managing Gaps among their Specification, Implementation, and Environment. Naoshi Uchihira (Toshiba)
Thu, Nov 26 PM  CAS(1)
13:30 - 14:45
(4) 13:30-13:55 Hierarchical Abstraction of Nonlinear Oscillator Macromodels Jaijeet Roychowdhury (Univ. of California, Berkeley)
(5) 13:55-14:20 A New FDTD Algorithm Based on Alternating-Direction Explicit (ADE) Method Shuichi Aono (SESAME Tech Inc.), Masaki Unno, Hideki Asai (Shizuoka Univ.)
(6) 14:20-14:45 Parallel-Distributed Block Latency Insertion Method (Block-LIM) for Fast Transient Simulation of Tightly Coupled Transmission Lines Yuta Inoue, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.)
Thu, Nov 26 PM  CST Invited Talk
15:00 - 15:50
  -  
(7) 15:00-15:50 [Invited Talk]
Probabilic Timed CEGAR
Atshushi Morimoto, Ryota Komagata, Satoshi Yamane (Kanazawa Univ.)
Thu, Nov 26 PM  CST Invited Talk
16:00 - 16:50
(8) 16:00-16:50 [Invited Talk]
Computational Complexity Analysis and Algorithms Design for Combinatorial Problems
Toshimasa Watanabe (Hiroshima Univ.)
Fri, Nov 27 AM  CST(2)
09:30 - 10:45
(9) 09:30-09:55 Model and Model Checking of Embedded Systems using Probablistic Game Theory Shouta Koshida, Satoshi Yamane (Kanazawa Univ.)
(10) 09:55-10:20 Model Checking of subclass of PTCTL by Probabilistic Timed REGAR Masaki Takahashi, Atsushi Morishita, Satoshi Yamane (Kanazawa Univ)
(11) 10:20-10:45 Diagnosis of Discrete Event Systems Modeled by Mealy Automata with Nondeterministic Output Functions Shigemasa Takai, Toshimitsu Ushio (Osaka Univ.)
Fri, Nov 27 PM  CAS(2)
13:00 - 14:15
(12) 13:00-13:25 Design and Evaluation of Graphics Accelerator System for Mobile Appliances Yasushi Nagai, Toru Owada (Hitachi), Tetsuo Takagi (Hitachi AD), Isao Takita (Hitachi)
(13) 13:25-13:50 Universal Test Sets for Reversible Circuits Satoshi Tayu, Shota Fukuyama, Shuichi Ueno (Tokyo Inst. of Tech.)
(14) 13:50-14:15 ILP Formulation of Graph Embedding and Its Application to LSI Routing Keisuke Inoue (JAIST/JSPS), Mineo Kaneko (JAIST)
Fri, Nov 27 PM  CST(3)
14:25 - 15:40
(15) 14:25-14:50 A Method to Determine Firing Times of Transitions for Timed Petri Nets by Introducing Stochastic Decision Rules Yoshimasa Miwa (Yamaguchi Univ.), Chen Li (Univ. of Tokyo), Qi-Wei Ge, Hiroshi Matsuno (Yamaguchi Univ.)
(16) 14:50-15:15 Experimental Evaluation of Asynchronous Genetic Algorithms on Line Topology Hayato Miyagi, Morikazu Nakamura (Univ. of the Ryukyus)
(17) 15:15-15:40 The Design of distributed algorithm for information gathering by using Petri Net Shin'nosuke Yamaguchi (Kyushu Inst. of Tech.), Katsumi Wasaki, Yasunari Shidama (Shinshu Univ)
Fri, Nov 27 PM  CST(4)
15:50 - 17:30
(18) 15:50-16:15 On Refactoring of Free-Choice Workflow Nets to Well-Structured Workflow Nets Yuki Kuroda, Shingo Yamaguchi, Minoru Tanaka (Yamaguchi Univ)
(19) 16:15-16:40 Application of a Consensus Problem to Distributed Fair QoS Control in Multi-tier Server Systems Naoki Hayashi, Toshimitsu Ushio, Takafumi Kanazawa (Osaka Univ.)
(20) 16:40-17:05 On Choreography Realization by Using Petri Nets Toshiyuki Miyamoto (Osaka Univ.), Taku Fujii (Ogis-RI)
(21) 17:05-17:30 Minimum Realization of Condition/Event Net Exhibiting Specified Behavior Susumu Hashizume, Tomoyuki Yajima, Katsuaki Onogi (Nagoya Univ.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
CAS Technical Committee on Circuits and Systems (CAS)   [Latest Schedule]
Contact Address Hiroshi YAMAZAKI (Fujitsu Laboratories Ltd.)
TEL +81-45-473-5801
E--mail: si 
CST Technical Committee on Concurrent Systems Technology (CST)   
Contact Address Shingo Yamaguchi(Graduate School of Science and Engineering, Yamaguchi University)
TEL: 0836-85-9510, FAX: 0836-85-9501
E--mail: ngu-u 
Announcement Latest information will be presented on the homepage:
http://www.ieice.org/~cst/


Last modified: 2009-09-25 19:08:05


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Presentation and Participation FAQ] (in Japanese)
 

[Return to CAS Schedule Page]   /  
 
 Go Top  Go Back   Prev CAS Conf / Next CAS Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan