Wed, Jan 25 AM FPGA Applications Chair: Atsushi Takahashi (Osaka Univ.) 10:00 - 12:05 |
(1) VLD |
10:00-10:25 |
Hardware TCP/IP Stack FPGA IP Core for Accelerating WEB Applications |
Kotoko Fujita, Nadav Bergstein, Hakaru Tamukoh, Masatoshi Sekine (TUAT) |
(2) VLD |
10:25-10:50 |
Detemination of Vocal Tract Shape on Voice Synthesis Circuit using Shift Register |
Keita Manabe, Rika Uegaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) |
(3) VLD |
10:50-11:15 |
Sound preprocessing circuit by consonant and vowel recognition system |
Keita Okamoto, Hakaru Tamukoh, Masatoshi Sekine (TUAT) |
(4) VLD |
11:15-11:40 |
Two Dimensional Array Processor for Moving Object Tracking using Synchronous Data Shift |
Takatosi Uchizono, Kazuya Osaku, Akinobu Tsuyuki, Zhu Li, Yoichi Tomioka, Hitoshi Kitazawa (TUAT) |
(5) VLD |
11:40-12:05 |
An Image Recognition System with Hierarchical Feature Learning Function |
Masahiro Ariizumi, Baku Ogasawara, Hakaru Tamukoh, Masatoshi Sekine (TUAT) |
Wed, Jan 25 PM Reconfigurable and Real time Processing Chair: Takeshi Takenaka (NEC) 13:30 - 14:45 |
(6) RECONF |
13:30-13:55 |
On a Decomposed MTMDDs for CF Machine |
Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) |
(7) CPSY |
13:55-14:20 |
An IPC Control Mechanism for Real-Time Processing on a Prioritized SMT Processor |
Kensuke Kaneda, Kohei Matsumoto, Nobuyuki Yamasaki (Keio Univ) |
(8) CPSY |
14:20-14:45 |
Extension of ITRON Specification OS for Multithreaded Processors |
Rikuhei Ueda, Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) |
Wed, Jan 25 PM Network Applications Chair: Nobuki Kajiwara (Renesas Electronics) 14:55 - 16:10 |
(1) CPSY |
14:55-15:20 |
Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router |
Takeo Nakamura, Hiroki Matsutani (Keio Univ.), Mitihiro Koibuchi (NII), Kimiyoshi Usami (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.) |
(2) RECONF |
15:20-15:45 |
A Proposal of Signal Integrity Improvement Method Using Impedance-reconfiguration Technique |
Moritoshi Yasunaga, Hiroki Shimada, Shohei Akita, Takuya Adachi, Hidetoshi Ishijima, Yusuke Kuribara (Univ. of Tsukuba) |
(3) CPSY |
15:45-16:10 |
A bandwidth control scheme based on a traffic analysis for an on-chip router |
Daiki Yamazaki, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) |
Wed, Jan 25 PM Dynamically Reconfigurable Computing and Robots Chair: Akihisa Yamada (Sharp) 16:20 - 18:00 |
(4) RECONF |
16:20-16:45 |
A Fast Approximate Solution of Energy Efficient Network Topology Using Reconfigurable Processor, STP |
Akiko Hirao, Hidetoshi Takeshita, Haruka Yonezu, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.) |
(5) RECONF |
16:45-17:10 |
Architecture and estimation of reconfigurable processor for multimedia processing |
Asuka Hayashi, Shuu'ichirou Yamamoto, Hideo Maejima (Tokyo Tech) |
(6) VLD |
17:10-17:35 |
Robot Control Unit by Using Dynamically Reconfigurable SU(3) Spin Circuit |
Yusaku Yamazaki, Takuya Suzuki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) |
(7) VLD |
17:35-18:00 |
A Mobile Robot System using Intelligent Circuit in Silicon |
Takuya Suzuki, Yusaku Yamazaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) |
Thu, Jan 26 AM Hi-level Synthesis and Arithmetic Applications(1) Chair: Hiroki Matsutani (Keio Univ.) 09:00 - 10:15 |
(8) VLD |
09:00-09:25 |
Merge of Functions in High-Level Synthesis using Assembly Codes as Intermediate Representation |
Fumiaki Takashima, Nagisa Ishiura, Makoto Orino (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) |
(9) VLD |
09:25-09:50 |
High-Level Synthesis of Hardware Relinkable to Software |
Makoto Orino, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Fumiaki Takashima (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) |
(10) RECONF |
09:50-10:15 |
The Estimation and Experiments of The Hardware Design Method from The UML Modeling Diagrams |
Daiki Kano, Ryota Yamazaki (Tokai Univ), Naohiko Shimizu (Tokai Univ/IP ARCH) |
Thu, Jan 26 AM Hi-level Synthesis and Arithmetic Applications(2) Chair: Hiroyuki Tomiyama (Ritsumeikan Univ.) 10:25 - 11:40 |
(11) VLD |
10:25-10:50 |
Interconnect Reduction in Binding Procedure of HLS |
Hao Cong, Song Chen, Takeshi Yoshimura (Waseda Univ.) |
(12) VLD |
10:50-11:15 |
A residue - weighted number conversion algorithm based on signed-digit arithmetic for a three-moduli set |
Masaya Arai, Yuuki Tanaka, Shugang Wei (Gunma Univ.) |
(13) VLD |
11:15-11:40 |
Error Checker using Binary tree structure of Residue Signed-Digit Additions |
Qian Liu, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) |
Thu, Jan 26 PM GPU and HPC Chair: Hideharu Amano(Keio Univ.) 12:40 - 15:10 |
(14) CPSY |
12:40-13:05 |
Discussion of Performance Prediction Model for Symmetric Block Ciphers on CUDA |
Naoki Nishikawa, Keisuke Iwai, Takakazu Kurokawa (NDA) |
(15) RECONF |
13:05-13:30 |
Fine-grained Adaptive Power Management for Energy Efficient GPU computing |
Makoto Murasaki, Tsuyoshi Hamada, Felipe A. Cruz (NACC) |
(16) CPSY |
13:30-13:55 |
development and evaluation of ParaRuby: a distributed GPGPU framework using Ruby |
Ryo Nakamura, Masato Yoshimi, Mitsunori Miki (Doshisha Univ.) |
(17) CPSY |
13:55-14:20 |
Implementation and its Evaluation of Distributed PC Grid System |
Junji Umemoto, Hiroyuki Ebara, Bunryu U (Kansai Univ.) |
(18) VLD |
14:20-14:45 |
Implementation of Numerical Circuit on 3D FPGA-Array |
Kenichi Takahashi, Jiang Li, Yusuke Atsumari, Shunsuke Shimazaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) |
(19) RECONF |
14:45-15:10 |
Partial Reconfiguration and Its Application on a PC-FPGA Hybrid Cluster |
Ryo Ozaki, Akira Uejima, Masaki Kohata (Okayama Univ. of Sci.) |
Thu, Jan 26 PM Reconfigurable Devices Chair: Moritoshi Yasunaga (Univ. of Tsukuba) 15:25 - 17:05 |
(20) RECONF |
15:25-15:50 |
Evaluation of Improvement Techniques for Placement and Routing on MPLD : a New Reconfigurable Device |
Ken Taomoto, Masato Inagi, Hideyuki Kawabata, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura, Masatoshi Nakamura (Hiroshima City Univ) |
(21) RECONF |
15:50-16:15 |
0.18 um process optically reconfigurable gate array VLSI |
Takahiro Watanabe, Minoru Watanabe (Shizuoka Univ.) |
(22) RECONF |
16:15-16:40 |
Recovery experiments from a laser array failure in an optically reconfigurable gate array using a reconfiguration speed-adjustment analog bit |
Takashi Yoza, Minoru Watanabe (Shizuoka Univ.) |
(23) VLD |
16:40-17:05 |
Study of pattern area and reconfigurable logic circuit with DG/CNT transistor |
Takamichi Hayashi, Shigeyoshi Watanabe (SIT) |