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13:00-13:05 |
Opening ( 5 min. ) |
Mon, Nov 28 PM 13:05 - 14:45 |
(1) VLD |
13:05-13:30 |
Development of ASIC Prototype Chip Evaluation System using FPGA-SoM |
Masashi Imai (Hirosaki Univ.), Kenji Kise (Tokyo Tech.), Tomohiro Yoneda (NII) |
(2) VLD |
13:30-13:55 |
A Study on Co-Optimization of logical structure and bit-line placement for Parallel Prefix Adders |
Mineo Kaneko (JAIST) |
(3) VLD |
13:55-14:20 |
A Routing Method by SAT for Set-Pair Routing Problem |
Koki Nagakura, Rintaro Yokoya, Kunihiro Fujiyoshi (Tokyo Univ of A and T) |
(4) VLD |
14:20-14:45 |
A Study of a Design Methodology for Various CGRA based on Diplomacy |
Takuya Kojima (UTokyo/JST PRESTO), Makoto Saito, Hiroshi Nakamura (UTokyo) |
Mon, Nov 28 PM 13:00 - 14:00 |
(5) |
13:00-14:00 |
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Mon, Nov 28 PM 14:00 - 16:15 |
(6) |
14:00-16:15 |
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Mon, Nov 28 PM 15:00 - 15:50 |
(7) DC |
15:00-15:25 |
On reduction of test patterns for a Multiplier Using Approximate Computing |
Shogo Tokai, Daichi Akamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ) |
(8) DC |
15:25-15:50 |
A 6T-8T hybrid SRAM for reducing the power of neural network by lowing the operating voltage |
Ruoxi Yu, Kazuteru Namba (Chiba Univ.) |
Mon, Nov 28 PM 16:15 - 18:00 |
(9) |
16:15-18:00 |
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Tue, Nov 29 AM 09:15 - 10:30 |
(10) DC |
09:15-09:40 |
A Don't Care Filling Method of control signals for controllers to Maximize the Number of Distinguishable Hard ware Element Pairs |
Yui Otsuka, Yuya Chida, Xu Haofeng, Toshinori Hosokawa (Nihon Univ.), Kouji Yamazaki (Meiji Univ.) |
(11) DC |
09:40-10:05 |
A Test Generation Merhod Based on Design for Diagnosability at RTL |
Yuya Chida, Toshinori Hosokawa (Nihon univ.), Koji Yamazaki (Meiji Univ.) |
(12) DC |
10:05-10:30 |
A Seed Generation Method for Multiple Random Pattern Resistant Stuck-at Faults in Built-In Self-Test |
Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) |
Tue, Nov 29 AM 10:45 - 12:00 |
(13) RECONF |
10:45-11:10 |
FPGA-based Accelerators System with Autonomous DMA Engine |
Tomoya Yokono, Yoshiro Yamabe, Kenji Tanaka, Yuki Arikawa, Teruaki Ishizaki (NTT) |
(14) RECONF |
11:10-11:35 |
A Message Passing Interface Library for High-Level Synthesis on M-KUBOS Multi-FPGA systems |
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.) |
(15) RECONF |
11:35-12:00 |
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12:00-13:15 |
Lunch Break ( 75 min. ) |
Tue, Nov 29 PM 13:15 - 14:05 |
(16) |
13:15-14:05 |
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Tue, Nov 29 PM 14:15 - 15:30 |
(17) ICD |
14:15-14:40 |
Method of Halved Interaction Elements with Regularity Arrangement that achieves Independent Double Systems for Scalable Fully Coupled Annealing Processing |
Shinjiro Kitahara, Akari Endo, Taichi Megumi, Takayuki Kawahara (TUS) |
(18) ICD |
14:40-15:05 |
Evaluating system level security of cryptography module |
Takumi Matsumaru, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuji Miki, Makoto Nagata (Kobe Univ.) |
(19) ICD |
15:05-15:30 |
Evaluation of power delivery networks in secure semiconductor systems |
Masaru Mashiba, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuzi Miki, Makoto Nagata (Kobe Univ.) |
Tue, Nov 29 PM 15:45 - 17:25 |
(20) VLD |
15:45-16:10 |
NA |
Tomokazu Yoshimura, Shirai Tatsuhiko, Masashi Tawada, Nozomu Togawa (Waseda Univ.) |
(21) VLD |
16:10-16:35 |
N/A |
Soma Kawakami (Waseda Univ.), Dema Ba, Kentaro Ohno, Satoshi Yagi, Junji Teramoto (NTT), Nozomu Togawa (Waseda Univ.) |
(22) VLD |
16:35-17:00 |
N/A |
Keisuke Fukada (Waseda Univ.), Matthieu Parizy (Waseda Univ./Fujitsu LTD.), Yoshinori Tomita (Fujitsu LTD.), Nozomu Togawa (Waseda Univ.) |
(23) VLD |
17:00-17:25 |
N/A |
Yuta Yachi, Masashi Tawada, Nozomu Togawa (Waseda Univ.) |
Tue, Nov 29 PM 17:40 - 18:30 |
(24) |
17:40-18:30 |
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Wed, Nov 30 AM 09:30 - 11:10 |
(25) VLD |
09:30-09:55 |
Development of 65nm-Cryo-CMOS Circuit Design Library |
Toshitsugu Sakamoto, Makoto Miyamura, Kazunori Funahashi, Koichiro Okamoto, Munehiro Tada (NBS), Takahisa Tanaka, Ken Uchida (Tokyo Univ.), Hiroki Ishikuro (Keio Univ.) |
(26) VLD |
09:55-10:20 |
Proposal of analytical expression for optimal store time of MTJ-based non-volatile flip-flops |
Daiki Yokoyama, Kimiyoshi Usami (SIT), Aika Kamei, Hideharu Amano (Keio Univ.) |
(27) VLD |
10:20-10:45 |
A fast SRAF optimization used LUT based point intensity calculation |
Sota Saito, Atsushi Takahashi (Tokyo Tech) |
(28) VLD |
10:45-11:10 |
Mask Optimization Using Voronoi Partition and Iterative Improvement |
Naoki Nonaka, Yukihide Kohira (Univ. of Aizu), Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) |
Wed, Nov 30 AM 09:30 - 11:10 |
(29) ICD |
09:30-09:55 |
A contact angle estimation method using two coplanar capacitive sensors of different sizes |
Tsubasa Furuta, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (USP) |
(30) ICD |
09:55-10:20 |
Design of Digital Phase-Locked Loop Circuit based on 3rd-Order MASH ΔΣ FDC for Low In-Band Phase Noise |
Ryoga Iwashita, Zule Xu, Masaru Osada, Ryoya Shibata, Yo Kumano, Tetsuya Iizuka (UTokyo) |
(31) ICD |
10:20-10:45 |
Deep Learning-based Hierarchical Object Detection System for High-Resolution Images |
Yusei Horikawa, Makoto Sugaya, Renpei Yoshida, Kazuma Mashiko, Tetsuya Matsumura (Nihon Univ.) |
(32) ICD |
10:45-11:10 |
Prototype and evaluation of 4-input variable logic circuit with FGC using neuron CMOS inverter |
Shoma Ito, Daishi Nishiguchi, Masaaki Fukuhara (Tokai Univ.) |
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11:10-12:40 |
Lunch Break ( 90 min. ) |
Wed, Nov 30 PM 12:40 - 13:20 |
(33) |
12:40-13:20 |
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Wed, Nov 30 PM 13:20 - 14:10 |
(34) |
13:20-14:10 |
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Wed, Nov 30 PM 14:20 - 15:35 |
(35) DC |
14:20-14:45 |
On the performance evaluation of a PUF circuit using the Delay Testable Circuit under temperature effects |
Eisuke Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) |
(36) DC |
14:45-15:10 |
Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC |
Keigo Takami (Tokushima Univ. Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) |
(37) DC |
15:10-15:35 |
FPGA Implementation and Area Evaluation of JTAG Access Mechanism Using Lightweight One-Time Password Authentication Scheme |
Hisashi Okamoto, Jun Ma, Senling Wang, Hiroshi Kai, Hiroshi Takahashi (Ehime Univ), Akihiro Shimizu (Kochi Univ. of Technology) |
Wed, Nov 30 PM 14:45 - 15:35 |
(38) |
14:45-15:10 |
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(39) |
15:10-15:35 |
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Wed, Nov 30 PM 15:50 - 17:30 |
(40) RECONF |
15:50-16:15 |
Design and Trial Production of Stochastic Resonance Processor using Differential Input Buffer in FPGA |
Akihiko Tsukahara, Sung-Gwi Cho, Keita Tanaka, Akihiko Homma, Yoshinori Uchikawa (Tokyo Denki Univ.) |
(41) RECONF |
16:15-16:40 |
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(42) RECONF |
16:40-17:05 |
Evaluation of Model Quantization Method on Vitis-AI for Mitigating Adversarial Examples |
Yuta Fukuda, Kota Yoshida, Takeshi Fujino (Ritsumeikan Univ.) |
(43) RECONF |
17:05-17:30 |
Implementation of stereo matching with Kria SOM toward precise field crop height measurement |
Ryo Nakagawa, Yoshiki Yamaguchi (Univ. of Tsukuba), Iman Firmansyah (BRIN) |
Wed, Nov 30 PM 16:15 - 17:30 |
(44) VLD |
16:15-16:40 |
FPGA Implementation of Learned Image Compression |
Heming Sun (Waseda U), Qingyang Yi (UTokyo), Jiro Katto (Waseda U), Masahiro Fujita (UTokyo) |
(45) VLD |
16:40-17:05 |
NA |
Kota Hisafuru, Nozomu Togawa (Waseda Univ.) |
(46) VLD |
17:05-17:30 |
Error detection and countermeasures caused by hardware trojan inserted computers |
Takuro Kasai, Masashi Imai (Hirosaki Univ.) |