|
|
| Chair |
|
Tanemasa Asano |
| Vice Chair |
|
Toshihiro Sugii |
| Secretary |
|
Morifumi Ohno, Shigeru Kawanaka |
| Assistant |
|
Yuichi Matsui |
|
|
|
| Chair |
|
Hirofumi Hamamura |
| Vice Chair |
|
Nagisa Ishiura |
| Secretary |
|
Toshiyuki Shibuya, Hiroyuki Ochi |
|
| Conference Date |
Mon, Sep 25, 2006 13:30 - 16:15
Tue, Sep 26, 2006 10:00 - 16:40 |
| Topics |
Process, Device, Circuit Simulation, etc. |
| Conference Place |
|
| Transportation Guide |
http://www.jspmi.or.jp/ |
Mon, Sep 25 PM
13:30 - 16:15 |
| (1) |
13:30-13:55 |
Sensitivity of CMOS Image Sensor and Scaling |
YunKyung Kim, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo) |
| (2) |
13:55-14:20 |
Peak Power Reduction in LSI by Clock Scheduling |
Yosuke Takahashi, Atsushi Takahashi (Tokyo Tech) |
| (3) |
14:20-14:45 |
To be announced |
Ryo Tanabe, Yoshio Ashizawa, Hideki Oka (Fujitsu Laboratories) |
| (4) |
14:45-15:10 |
[Invited Talk]
Report on 2006 DAC
-- Low Power Design Methodology -- |
Shigeru Kuriyama (STARC) |
| |
15:10-15:30 |
Break ( 20 min. ) |
| (5) |
15:30-16:15 |
[Fellow Memorial Lecture]
To be announced |
Hitoshi Kitazawa (Tokyo Univ. of Agriculture and Technology) |
Tue, Sep 26 AM
10:00 - 11:40 |
| (6) |
10:00-10:25 |
A Processor for Genetic Algorithm using Dynamically Reconfigurable Memory |
Akihiko Tsukahara, Akinori Kanasugi (Tokyo Denki Univ.) |
| (7) |
10:25-10:50 |
To be announced |
Yoshio Ashizawa, Hideki Oka (FUJITSU LABORATORIES) |
| (8) |
10:50-11:15 |
Global Identification of Variability Factors and Its Application to the Statistical Worst-Case Model Generation |
Katsumi Eikyu, Takeshi Okagaki, Motoaki Tanizawa, Kiyoshi Ishikawa, Osamu Tsuchiya (Renesas) |
| (9) |
11:15-11:40 |
Modeling of Discrete Dopant Effects on Threshold Voltage Shift by Random Telegraph Signal |
Ken'ichiro Sonoda, Kiyoshi Ishikawa, Takahisa Eimori, Osamu Tsuchiya (Renesas Technology Corp.) |
| |
11:40-13:00 |
Lunch Break ( 80 min. ) |
Tue, Sep 26 PM
13:00 - 16:40 |
| (10) |
13:00-13:25 |
Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations |
Takahisa Kanemura, Takashi Izumida, Nobutoshi Aoki, Masaki Kondo, Sanae Ito, Toshiyuki Enda, Kimitoshi Okano, Hirohisa Kawasaki, Atsushi Yagishita, Akio Kaneko, Satoshi Inaba, Mitsutoshi Nakamura, Kazunari Ishimaru, Kyoichi Suguro, Kazuhiro Eguchi (Toshiba Corp.) |
| (11) |
13:25-13:50 |
To be announced |
Yoshimasa Yoshioka, Yasuhisa Omura (Kansai Univ.) |
| (12) |
13:50-14:15 |
A Novel Asymmetric Raised Source/Drain Extension Structure for 32nm-node MOSFETs
-- An ultimate planar MOSFET -- |
Tsutomu Imoto, Yasushi Tateshita, Toshio Kobayashi (SONY) |
| |
14:15-14:35 |
Break ( 20 min. ) |
| (13) |
14:35-15:00 |
To be announced |
Tsuyoshi Yamamura, Shingo Sato, Yasuhisa Omura (Kansai Univ.) |
| (14) |
15:00-15:25 |
To be announced |
Hideaki Tsuchiya, Kazuya Fujii, Takashi Mori, Tanroku Miyoshi (Kobe Univ.) |
| (15) |
15:25-15:50 |
To be announced |
Hideki Minari, Nobuya Mori (Osaka Univ.) |
| (16) |
15:50-16:15 |
Quantum Electron Transport Modeling in Nano-Scale Devices Based on Multiband Non-Equilibrium Green's Funtion Method |
Helmy Fitriawan, Satofumi Souma, Matsuto Ogawa, Tanroku Miyoshi (Kobe Univ.) |
| (17) |
16:15-16:40 |
To be announced |
Masami Hane, Takeo Ikezawa, Michihito Kawada (NEC), Tatsuya Ezaki (Hiroshima Univ.), Toyoji Yamamoto (MIRAI-ASET) |
| Contact Address and Latest Schedule Information |
| SDM |
Technical Committee on Silicon Device and Materials (SDM) [Latest Schedule]
|
| Contact Address |
Yasushiro Nishioka (Nihon University, College of Science and Technology)
TEL047-469-6482,FAX047-467-9504
E- :    e   t n-u ,a  cmsk  |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Shibuya Toshiyuki(Fujitsu Laboratories)
E-:bu    
Tel.044-754-2663 |
| Announcement |
You will see the latest information at the below WEB page.
http://www.ieice.org/~vld/ |
Last modified: 2006-07-26 18:17:16
|