Thu, Jan 18 AM Chair: Makoto Motomura (Hokkaido Univ) 09:15 - 10:30 |
(1) CPSY |
09:15-09:40 |
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Yugo Yamauchi, Kazusa Musha (Keio Univ.), Kudoh Tomohiro (Univ. of Tokyo), Hideharu Amano (Keio Univ.) |
(2) RECONF |
09:40-10:05 |
All Binarized Conventional Neural Network and its Implementation on an FPGA
-- FPT2017 Design Competition Report -- |
Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) |
(3) RECONF |
10:05-10:30 |
An Implementation of a Binarized Deep learning Neural Network on an FPGA using the Intel OpenCL |
Takumu Uyama, Tomoya Fujii, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara (Titech) |
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10:30-10:40 |
Break ( 10 min. ) |
Thu, Jan 18 AM 10:40 - 11:55 |
(4) CPSY |
10:40-11:05 |
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Kazutaka Ogihara (Fujitsu Lab.) |
(5) CPSY |
11:05-11:30 |
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Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) |
(6) CPSY |
11:30-11:55 |
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11:55-13:00 |
Lunch Break ( 65 min. ) |
Thu, Jan 18 PM 13:00 - 14:15 |
(7) VLD |
13:00-13:25 |
Reducing Power Consumption for Circuits Dedicated to Image Sharpening Processing using CMAs |
Kaori Tajima, Masahiro Inoue, Hiroyuki Baba, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.) |
(8) VLD |
13:25-13:50 |
Residue-weighted number conversion based on Signed-Digit arithmetic for a four moduli set |
Kouhei Yamazaki, Yuuki Tanaka, Shugang Wei (Gunma Univ.) |
(9) VLD |
13:50-14:15 |
Examination of the Normally-off using the stack circuit |
Kenji Sakamura (OPUGS), Kazutami Arimoto, Isao Kayano, Tomoyuki Yokogawa (OPU) |
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14:15-14:25 |
Break ( 10 min. ) |
Thu, Jan 18 PM 14:25 - 15:25 |
(10) CPSY |
14:25-15:25 |
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15:25-15:35 |
Break ( 10 min. ) |
Thu, Jan 18 PM Chair: Kazuya Tanigawa (Hiroshima City Univ.) 15:35 - 16:25 |
(11) RECONF |
15:35-16:00 |
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(12) RECONF |
16:00-16:25 |
Integrated Machine Code Monitor on FPGA |
Hiroaki Kaneko, Akinori Kanasugi (TokyoDenki Univ.) |
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16:25-16:35 |
Break ( 10 min. ) |
Thu, Jan 18 PM Chair: Hiroki Nakahara (Tokyo Tech) 16:35 - 17:25 |
(13) RECONF |
16:35-17:00 |
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Daichi Tanaka, Antoniette Mondigo, Kentaro Sano, Satoru Yamamoto (Tohoku Univ) |
(14) VLD |
17:00-17:25 |
Distributed Memory Architecture for High-Level Synthesis from Erlang |
Kagumi Azuma, Shoki Hamana, Hidekazu Wakabayashi, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) |
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17:25-18:00 |
Break ( 35 min. ) |
Thu, Jan 18 PM 18:00 - 20:00 |
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Fri, Jan 19 AM Chair: Kentaro Sano (Tohoku Univ.) 09:15 - 10:30 |
(15) RECONF |
09:15-09:40 |
FPGA Implementation of Stencil Computation Using Multi-threading with High-level Synthesis Based on Java Language |
Keitaro Yanai (TUAT), Yasunori Osana (Ryukyus Univ.), Hironori Nakajo (TUAT) |
(16) RECONF |
09:40-10:05 |
Overview of an HLS Framework Surpporting IoT/CPS Development |
Daichi Teruya, Hironori Nakajo (TUAT) |
(17) RECONF |
10:05-10:30 |
Automatic Conversion from Snort PCRE to Verilog HDL |
Masahiro Fukuda, Yasushi Inoguchi (JAIST) |
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10:30-10:40 |
Break ( 10 min. ) |
Fri, Jan 19 AM 10:40 - 11:55 |
(18) VLD |
10:40-11:05 |
Design and Implementation of 176-MHz WXGA 30-fps Real-time Optical Flow Processor |
Satoshi Kanda, Yu Suzuki, Masato Ito (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) |
(19) VLD |
11:05-11:30 |
A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT |
Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) |
(20) RECONF |
11:30-11:55 |
Total-ionizing-dose tolerance of an optically reconfigurable gate array |
Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.) |
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11:55-13:00 |
Lunch Break ( 65 min. ) |
Fri, Jan 19 PM 13:00 - 14:15 |
(21) RECONF |
13:00-13:25 |
FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights |
Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
(22) |
13:25-13:50 |
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(23) CPSY |
13:50-14:15 |
Accelerating Sequential Learning Algorithm OS-ELM Using FPGA-NIC |
Mineto Tsukada, Koya Mitsuzuka, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.) |
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14:15-14:25 |
Break ( 10 min. ) |
Fri, Jan 19 PM 14:25 - 15:40 |
(24) CPSY |
14:25-14:50 |
Accelerating Serialization Protocols for Network-Attached FPGAs |
Takuma Iwata, Koya Mitsuzuka, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.) |
(25) RECONF |
14:50-15:15 |
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(26) RECONF |
15:15-15:40 |
Circuit Partitioning for Stream Computing in Scalable Hardware Mechanism and its implementation on FPGAs |
Yoshio Murata, Hironori Nakajo (TUAT) |
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15:40-15:50 |
Break ( 10 min. ) |
Fri, Jan 19 PM 15:50 - 17:05 |
(27) |
15:50-16:15 |
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(28) VLD |
16:15-16:40 |
Reinforcing Generation of Control Flow Statements in Random Test System of C Compilers Based on Equivalence Transformation |
Mitsuyoshi Iwatsuji, Nagisa Ishiura (Kwansei Gakuin Univ.) |
(29) VLD |
16:40-17:05 |
Mutant Generation of Performance Tests for LLVM Back-Ends |
Kenji Tanaka, Nagisa Ishiura (Kwansei Gakuin Univ.), Masanari Nishimura, Akiya Fukui (Renesas) |