IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   Prev MSS Conf / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on Mathematical Systems Science and its Applications (MSS) [schedule] [select]
Chair Shingo Yamaguchi (Yamaguchi Univ.)
Vice Chair Toshiyuki Miyamoto (Osaka Inst. of Tech.)
Secretary Naoki Hayashi (Osaka Univ.), Jianquan Liui (NEC)
Assistant Masato Shirai (Shimane Univ.)

Technical Committee on Circuits and Systems (CAS) [schedule] [select]
Chair Norihiko Shinomiya (Soka Univ.)
Vice Chair Shinji Shimoda (Sony Semiconductor Solutions)
Secretary Daisuke Kasamatsu (Soka Univ.), Yasuhide Takase (Murata Manufacturing)
Assistant Nao Ito (NIT, Toyama college), Shunsuke Koshita (Hachinohe Inst. of Tech.), Hiroto Suzuki (Renesas Electronics)

Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Yuichi Sakurai (Hitachi)
Vice Chair Hiroyuki Tomiyama (Ritsumeikan Univ.)
Secretary Yukihiro Sasagawa (Socionext), Kenshu Seto (Kumamot Univ.)
Assistant Takuma Nishimoto (Hitachi)

Technical Committee on Signal Processing (SIP) [schedule] [select]
Chair Koichi Ichige (Yokohama National Univ.)
Vice Chair Akira Tanaka (Hokkaido Univ.), Kiyoshi Nishikawa (okyo Metropolitan Univ.)
Secretary Shoko Imaizumi (Chiba Univ.), Taizo Suzuki (Univ. of Tsukubaba)
Assistant Masanari Nakamura (Hokkaido Univ.), Sayaka Shiota (Tokyo Metropolitan Univ.)

Conference Date Thu, Jul 18, 2024 09:30 - 16:30
Fri, Jul 19, 2024 09:30 - 16:30
Topics  
Conference Place  
Sponsors This conference is co-sponsored by Hirosaki University and IEEE Signal Processing Society Tokyo Joint Chapter. This conference is technical co-sponsored by IEEE Circuits and Systems Society Japan Chapter(IEEE CASS JC), IEEE Signal Processing Society Tokyo Joint Chapter and APSIPA Japan Chapter.
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on VLD, CAS, SIP, MSS.
Due for Registration Please proceed the payment of registration fee by 3 days before the workshop date. The meeting URL will be sent from one of the secretaries of the committee via e-mail, just before the workshop date.

Thu, Jul 18 AM 
09:30 - 11:35
(1) 09:30-09:55 Study of instantaneous frequency estimation using finite order 2-D Hilbert transformer Yuka Shiraishi, Jun Obara (TUS), Yasunori Sugita (NUT), Naoyuki Aikawa (TUS)
(2) 09:55-10:20 Fast Processing Methods for Generalized Gaussian Functions Hirokazu Kamei, Soichiro Honda, Kohei Hayashi, Norishige Fukushima (NITech)
(3) 10:20-10:45 Image Quality Assessment for Detail Enhancement by Synthetic Image Normalization Soichiro Honda, HiroKazu Kamei, Kohei Hayashi, Norishige Fukushima (NITech)
(4) 10:45-11:10 A fine-tuning method using encrypted pre-trained model for Vision Transformer considering privacy protection Kouki Horio, Kiyoshi Nishikawa, Hitoshi Kiya (TMU)
(5) 11:10-11:35 A method for phase retrieval from STFT magnitude based on the Taylor series expansion of a modified Bargmann transform Kazuki Nishino, Takaaki Nara (UTokyo)
  11:35-13:00 Break ( 85 min. )
Thu, Jul 18 PM 
13:00 - 13:50
(6) 13:00-13:25 Analysis of Malicious Botnets and Disinfection by White-Hat Worms Using Mirai Source Code Yudai Yamamoto, Aoi Fukushima, Shingo Yamaguchi (Yamaguchi Univ.)
(7) 13:25-13:50 Proposal for an Immune Mechanism in Botnet Defense System Shingo Yamaguchi (Yamaguchi Univ.)
  13:50-14:00 Break ( 10 min. )
Thu, Jul 18 PM 
14:00 - 16:30
(8) 14:00-14:25 Measurement of Leakage based Strong PUF Operating at Ultra Low Voltage Using a Leakage Control Approach Shunkichi Hata, Kimiyoshi Usami (SIT)
(9) 14:25-14:50
(10) 14:50-15:15 NA Hibiki Nakanishi (Waseda Univ.), Kento Hasegawa, Seira Hidano, Kazuhide Fukushima (KDDI Research, Inc.), Kazuo Hashimoto, Nozomu Togawa (Waseda Univ.)
(11) 15:15-15:40 Evaluation of BSIM4 at cryogenic temperature using 65nm bulk transistor Shin Taniguchi, Michihiro Shintani (KIT)
(12) 15:40-16:05
(13) 16:05-16:30
Fri, Jul 19 AM 
09:30 - 11:35
(14) 09:30-09:55 Effect of Multiple Pedestrian Information on Machine Learning Indoor Location Estimation Nao Ito, Jin Kitsukawa, Kazuya Unjo (NIT, Toyama)
(15) 09:55-10:20 Design of LTCC-based Balanced BPF with Coupled-line Resonators and Ring Resonators Tatsuyoshi Tanii, Hiroki Matsuura, Koji Wada (UEC)
(16) 10:20-10:45 On Preparations of proofs of the existence of MMOs
-- Considerations from Urabe's Theorems, Piecewise Linear Models, and a Krawczyk Operator for Function Strips --
Hideaki Okazaki, Naohiko Inaba (SIT)
(17) 10:45-11:10 Estimation of Blood Components in Castle Using Near-Infrared Spectroscopy Marika Takeshima (TUS), Takahiro Natori (TU), Yuka Kawatus, Hisashi Nabenishi (KU), Naoyuki Aikawa (TUS)
(18) 11:10-11:35 On the impact of gaming in negawatt trading on the profits of retail electricity producers Takashi Yashiki, Norihiko Shinomiya (Soka Univ.)
  11:35-13:00 Break ( 85 min. )
Fri, Jul 19 PM 
13:00 - 14:40
(19) 13:00-13:25 An attempt to analyze time series data of convergence motion during 3D-maze video viewing Yoshinobu Maeda (Niigata Univ.), Masako Ishii (NUHW), Akira Tsukada (NIT, Toyama College)
(20) 13:25-13:50 A Prototype of 21 GHz Wideband Bandpass Filter using a Stub-Loaded Resonator and T-shape Stubs Hiroki Matsuura, Sho Kasai, Koji Wada (UEC)
(21) 13:50-14:15 An Examination of the Relationship between the Two-Stage Chebyshev Transmission Line Matching Circuit and the LC Matching Circuit Satoshi Tanaka, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.)
(22) 14:15-14:40 Operable Time Evaluation of FPGA-based Sensor Node with Capacitor Power Supply Varying Basic Circuit Resources Itsuki Fukumitsu, Akira Yamawaki (Kyutech)
  14:40-14:50 Break ( 10 min. )
Fri, Jul 19 PM 
14:50 - 16:30
(23) 14:50-15:15
(24) 15:15-15:40
(25) 15:40-16:05 A Routing Method for 2-Layer Comb-shaped Bottleneck Routing Problem Ryo Takata, Kunihiro Fujiyoshi (TUAT)
(26) 16:05-16:30

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
MSS Technical Committee on Mathematical Systems Science and its Applications (MSS)   [Latest Schedule]
Contact Address Masato Shirai (Shimane University)
E--mail: icis-u 
CAS Technical Committee on Circuits and Systems (CAS)   [Latest Schedule]
Contact Address CAS administrator Group
E--mail: cas-adn 
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Yukihiro Sasagawa (Socionext)
E--mail: vld-n24 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
SIP Technical Committee on Signal Processing (SIP)   [Latest Schedule]
Contact Address IEICE Technical Group on Signal Processing
Email: sip-n 


Last modified: 2024-06-26 00:01:29


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Presentation and Participation FAQ] (in Japanese)
 

[Return to CAS Schedule Page]   /   [Return to VLD Schedule Page]   /   [Return to SIP Schedule Page]   /   [Return to MSS Schedule Page]   /  
 
 Go Top  Go Back   Prev MSS Conf / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan