Mon, Jan 29 AM 10:30 - 12:10 |
(1) |
10:30-10:55 |
Random number generation on the Rocket core with a built-in LFSR |
Takayoshi Shikano, Shuichi Ichikawa (Toyohashi Tech.) |
(2) |
10:55-11:20 |
Suppression of output bit width growth in AFE stochastic computing units |
Daiki Seto, Naoki Fujieda (Aichi Inst. Tech.) |
(3) |
11:20-11:45 |
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(4) |
11:45-12:10 |
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12:10-13:30 |
Lunch Break ( 80 min. ) |
Mon, Jan 29 PM 13:30 - 14:20 |
(5) |
13:30-14:20 |
[Invited Talk]
Role of FPGAs in Quantum Network Architectures |
Fumiaki Mizuno (Keio Univ.) |
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14:20-14:40 |
Break ( 20 min. ) |
Mon, Jan 29 PM 14:40 - 16:20 |
(6) |
14:40-15:05 |
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(7) |
15:05-15:30 |
A Study of Low Latency Feedback Operation Architecture for Superconducting Qubit |
Takefumi Miyoshi (QuEL/e-trees), Keisuke Koike (e-trees), Kazuhisa Ogawa, Ryo Matsuda, Hidehisa Shiomi (Osaka Univ.), Shinichi Morisaka (Osaka Univ./QuEL), Yutaka Tabuchi (RIKEN), Makoto Negoro (Osaka Univ.) |
(8) |
15:30-15:55 |
An FPGA-based data compressor for state vector quantum simulators |
Kaijie Wei, Hideharu Amano (Keio Univ.), Ryohei Niwase (Tsukuba Univ.), Takefumi Miyoshi (WasaLabo), Yoshiki Yamaguchi (Tsukuba Univ.) |
(9) |
15:55-16:20 |
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16:20-16:35 |
Break ( 15 min. ) |
Mon, Jan 29 PM 16:35 - 17:50 |
(10) |
16:35-17:00 |
High-speed division circuits using BCD codes |
Fumiya Kanai, Yuki Tanaka (Gunma Univ.) |
(11) |
17:00-17:25 |
Derivation of an Evaluation Chip Spec suitable for Tester and Data Analysis
-- Toward comparative evaluation of latch-based and flip-flop-based circuits -- |
Tadaaki Tanimoto, Keizo Hiraga, Toshihiko Katou, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions) |
(12) |
17:25-17:50 |
Comparison of latch-based circuit and flip-flop-based circuit in actual device |
Kenji Takahashi, Tadaaki Tanimoto, Keizo Hiraga, Masayuki Hayashi, Takato Inoue, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions) |
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17:50-18:00 |
Break ( 10 min. ) |
Mon, Jan 29 PM 18:00 - 20:00 |
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Tue, Jan 30 AM 10:30 - 11:20 |
(13) |
10:30-10:55 |
Design space exploration for a CGRA architecture that efficiently handles the Systolic algorithm |
Hajime Takishita (Keio Univ.), Takuya Kojima (UTokyo), Hideharu Amano (Keio Univ.) |
(14) |
10:55-11:20 |
A Prototype Design of an Embedded Real-Time GPU |
Takafumi Tarui, Nobuyuki Yamasaki (Keio Univ.) |
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11:20-11:30 |
Break ( 10 min. ) |
Tue, Jan 30 PM 11:30 - 12:00 |
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12:00-13:20 |
Lunch Break ( 80 min. ) |
Tue, Jan 30 PM 13:20 - 14:10 |
(15) |
13:20-13:45 |
Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems |
Kei Mikami, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) |
(16) |
13:45-14:10 |
Implementation of External Memory Access for Binary Synthesis Using General-Purpose High-Level Synthesizer |
Sho Kishimoto, Nagisa Ishiukra (Kwansei Gakuin Univ.) |
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14:10-14:25 |
Break ( 15 min. ) |
Tue, Jan 30 PM 14:25 - 15:25 |
(17) |
14:25-14:50 |
Exploration of Acceleration of FPGA-based Linear Equation Solver using Approximate Division in Electronic Circuit Simulator |
Naoki Kakine, Shuto Yuya, Tetsuo Hironaka, Atsushi Kubota (HCU) |
(18) |
14:50-15:15 |
FPGA-Accelerated Random Forest for Real-Time IoT Intrusion Detection |
Qingyu Zeng, Yuko Hara (Tokyo Tech) |
(19) |
15:15-15:25 |
Comparison of Graph Data Structures for Breadth-First Search Accelerator HyGTA2 |
Jun Akimoto, Kazuya Tanigawa (Hiroshima City Univ), Kentaro Sano (Processor Research Team,RIKEN Center for Computational Science), Tetsuo Hironaka (Hiroshima City Univ) |