Thu, Sep 14 PM 13:30 - |
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13:30-13:40 |
( 10 min. ) |
Thu, Sep 14 PM 13:40 - 14:40 |
(1) |
13:40-14:40 |
[Invited Talk]
Virtual reconfigurable system by software |
Shuichi Takada (ArchiTek) |
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14:40-15:00 |
Break ( 20 min. ) |
Thu, Sep 14 PM 15:00 - 15:50 |
(2) |
15:00-15:25 |
Monitoring system for optically reconfigurable gate arrays under radiation environments |
Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) |
(3) |
15:25-15:50 |
Implementation of a sequential circuit onto an optically reconfigurable gate array VLSI without any crystal oscillator |
Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) |
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15:50-16:10 |
Break ( 20 min. ) |
Thu, Sep 14 PM Lightning Talk 16:10 - 17:00 |
(4) |
16:10-16:20 |
Building Simulation Environment for Reconfigurable Virtual Accelerator (ReVA) |
Shunya Kawai, Kazuki Yaguchi, Eriko Maeda (TUAT), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) |
(5) |
16:20-16:30 |
Integrating RISC-V Vector Extension and SMT for Embedded AI Workloads |
Hidetaro Tanaka, Shogo Takata, Hironori Nakajo (TUAT) |
(6) |
16:30-16:40 |
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(7) |
16:40-16:50 |
Implementation and Evaluation of a Hardware Accelerator using High-Speed Data Transfer with the Vector Register Sharing Mechanism |
Go Akamatsu, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) |
(8) |
16:50-17:00 |
Construction of Visualization Environment for CGRA Operation Verification |
Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura (UT) |
Fri, Sep 15 AM 09:30 - 10:45 |
(1) |
09:30-09:55 |
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(2) |
09:55-10:20 |
SATA burst data transfer pattern of state vector simulator |
Hideharu Amano, Wei Kaijie (Keio Univ.), Ryohei Nisawa (Univ. of Tsukuba), Takefumi Miyoshi (Wasalabo), Yoshiki Yamaguchi (Univ. of Tsukuba) |
(3) |
10:20-10:45 |
* |
Shintaro Kawasaki, Mizuki Ito, Yoshiki Yamaguchi () |
Fri, Sep 15 PM 10:45 - 12:15 |
(4) |
10:45-12:15 |
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12:15-13:25 |
Break ( 70 min. ) |
Fri, Sep 15 PM 13:25 - 15:05 |
(5) |
13:25-13:50 |
Implementation and Evaluation of a Hardware Accelerator via Vector Register Sharing Mechanism for Massive Data Transfer |
Michiya Kato, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi MIyoshi (Wasarabo LLC), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) |
(6) |
13:50-14:15 |
Abstraction of Processor-FPGA Communication in Reconfigurable Virtual Accelerator (ReVA) |
Eriko Maeda, Kazuki Yaguchi, Shunya Kawai, Daichi Teruya (TUAT), Yasunori Osana (Kumamoto Univ.), Takehumi Miyoshi (Wasalabo), Hironori Nakajo (TUAT) |
(7) |
14:15-14:40 |
Library Development for RISC-V FPGA SoCs |
Takuya Kojima (UTokyo/JST PRESTO), Yosuke Yanai (Keio Univ.), Hayate Okuhara (NUS), Hideharu Amano (Keio Univ.), Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) |
(8) |
14:40-15:05 |
On the FPGA Implementation of a Lightweight Neural Network for Point Clouds |
Keisuke Sugiura, Hiroki Matsutani (Keio Univ.) |
Fri, Sep 15 PM 15:05 - 15:05 |
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15:05-15:15 |
( 10 min. ) |
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15:15-15:20 |
( 5 min. ) |
Fri, Sep 15 PM 15:30 - 15:20 |
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15:30-17:00 |
( 90 min. ) |