Thu, Jan 29 AM 08:35 - 10:15 |
(1) CPSY |
08:35-08:55 |
Performance Acceleration of Document-Oriented Stores Using GPUs |
Shin Morishima, Hiroki Matsutani (Keio Univ.) |
(2) CPSY |
08:55-09:15 |
Accelerating NOSQLs using FPGA NIC and In-Kernel Key-Value Cache |
Korechika Tamura, Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.) |
(3) CPSY |
09:15-09:35 |
An Online Outlier Detector for FPGA NICs |
Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.) |
(4) CPSY |
09:35-09:55 |
Turbo Boost Router: An On-Chip Router Supporting Deterministic and Adaptive Routings |
Natsuki Homma, Go Matsumura (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.) |
(5) CPSY |
09:55-10:15 |
NoC Architecture with Priority-based Packet Overtaking and Resource Control |
Shuhei Otsuki, Keigo Mizotani, Masayoshi Takasu (Keio Univ.), Daiki Yamazaki (Sony), Nobuyuki Yamasaki (Keio Univ.) |
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10:15-10:35 |
Break ( 20 min. ) |
Thu, Jan 29 AM 10:25 - 11:25 |
(6) RECONF |
10:25-10:45 |
Radiation tolerance of parallel configuration of optically reconfigurable gate arrays |
Hiroyuki Ito, Retsu Moriwaki, Minoru Watanabe (Shizuoka Univ.) |
(7) RECONF |
10:45-11:05 |
Circuit Design and Valuation of Reconfigurable Logic Circuit. |
Junki Kato, Shigeyoshi Watanabe, Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura (SIT) |
(8) RECONF |
11:05-11:25 |
Exploring 3D FPGA Architectures to Minimize the Number of Inter-layer Connections |
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
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11:25-12:35 |
Lunch Break ( 70 min. ) |
Thu, Jan 29 PM 12:45 - 13:35 |
(9) RECONF |
12:45-13:35 |
[Invited Talk]
Human Friendly Robot Based on Ontologies |
Takahira Yamaguchi (Keio Univ.) |
Thu, Jan 29 PM 13:50 - 14:50 |
(10) |
13:50-14:10 |
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(11) |
14:10-14:30 |
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(12) |
14:30-14:50 |
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14:50-15:05 |
Break ( 15 min. ) |
Thu, Jan 29 PM 15:05 - 16:25 |
(13) RECONF |
15:05-15:25 |
An AWF Digital Spectrometer for a Radio Telescope |
Hiroki Nakahara (Ehime Univ.), Hiroyuki Nakanishi (Kagoshima Univ.), Kazumasa Iwai (NAOJ) |
(14) RECONF |
15:25-15:45 |
Small Bandwidth Compression Hardware Exploited Distribution of Length of Prediction Residual |
Tomohiro Ueno, Ryo Ito, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) |
(15) RECONF |
15:45-16:05 |
Inter-Cube Data-Exchanging for Custom Fluid Computing Machine Based on Building-Cube Method |
Tomoya Ueno, Tomohiro Ueno, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) |
(16) RECONF |
16:05-16:25 |
FPGA Implementation of a High Time Resolution Signal Generation Circuit for PWM |
Shun Kashiwagi, Daiki Mitsutake, Hironobu Taniguchi, Yuichiro Shibata, Kiyoshi Oguri, Hidenori Maruta, Fujio Kurokawa (Nagasaki Univ.) |
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16:25-16:40 |
Break ( 15 min. ) |
Thu, Jan 29 PM 16:40 - 18:20 |
(17) VLD |
16:40-17:00 |
Study on Clock Tree Delay Analysis Mechanism |
Goro Suzuki, Ryutaro Takeda (Kitakyushu Univ.) |
(18) VLD |
17:00-17:20 |
Temperature sensor applying Body Bias in Silicon-on-Thin-BOX |
Tsubasa Kosaka, Shohei Nakamura, Kimiyoshi Usami (S.I.T.) |
(19) VLD |
17:20-17:40 |
A Dual-mode Scheduling Strategy for Task Graphs with Data Parallelism |
Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.) |
(20) VLD |
17:40-18:00 |
Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits |
Toshihiro Takeshita, Shinichi Nishizawa, AKM Mahfuzul Islam, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ) |
(21) VLD |
18:00-18:20 |
CF3: Test suite for arithmetic optimization of C compilers |
Yusuke Hibino, Nagisa Ishiura (KGU) |
Fri, Jan 30 AM 08:30 - 10:10 |
(22) RECONF |
08:30-08:50 |
Discussion on power performance optimization for stream processing on an FPGA accelerator |
Kota Fukumoto, Koji Okina, Rie Soejima, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
(23) RECONF |
08:50-09:10 |
A proposal of a stream image compression architecture using neural networks |
Kaoru Hamasaki, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
(24) RECONF |
09:10-09:30 |
Intrusion Detection in High-Speed Networks with a Multi-Byte Transition NFA |
Shin'ichi Wakabayashi, Tomoaki Hashimoto, Ryohei Koishi, Hiroki Takaguchi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.) |
(25) RECONF |
09:30-09:50 |
Implementation and Evaluation of the Low-level Communication Mechanism on FLOPS-2D |
Katsuki Kyan, Makoto Arakaki, Yusuke Hirai, Hiroki Nakasone (Univ. of the Ryukyus), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.), Yasunori Osana (Univ. of the Ryukyus) |
(26) RECONF |
09:50-10:10 |
A feasibility study on implementing numerical applications on FPGAs using Vivado HLS |
Hiroki Nakasone, Yasunori Osana, Yasunori Nagata (Univ of Ryukyu) |
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10:10-10:30 |
Break ( 20 min. ) |
Fri, Jan 30 AM 10:30 - 12:10 |
(27) VLD |
10:30-10:50 |
Error detection using residue signed-digit number arithmetic for arithmetic circuits |
Yoshitomo Nema, Yuuki Tanaka, Kazuhiro Motegi, Shugang Wei (Gunma Univ) |
(28) VLD |
10:50-11:10 |
A Hardware Trojan Detection Method based on Trojan net features |
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(29) VLD |
11:10-11:30 |
The proposal of the convex area maze router on LSI design automation |
Yohei Horino, Jun Hirayama, Yukiko Ohishi, Toshiyuki Tsutsumi (Meiji Univ.) |
(30) VLD |
11:30-11:50 |
Detecting Missed Arithmetic Optimization Opportunities Using Random Testing of C Compilers |
Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ.) |
(31) VLD |
11:50-12:10 |
An FPGA Implementation of Deep Convolutional Neural Network using Synchronous Shift Data Transfer |
Li Ning, Yoichi Tomioka, Hitoshi Kitazawa (TUAT) |
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12:10-13:20 |
Lunch Break ( 70 min. ) |
Fri, Jan 30 PM 13:20 - 14:40 |
(32) CPSY |
13:20-13:40 |
Implementation of Sparse Matrix-Vector Multiplication on GPU and Its Application to the Conjugate Gradient Method |
Shotaro Asano, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
(33) CPSY |
13:40-14:00 |
Relaxing constraint conditions in parallelizing compiler based on a polyhedral model |
Toma Ogata, Hidehiro Nakano, Arata Miyauchi (Tokyo City Univ.) |
(34) CPSY |
14:00-14:20 |
Acceleration of Big Data Partitioning with Multiple FPGA boards |
Ryu Kudo, Saori Sudo, Yasin Oge (UEC), Yuta Terada (AVAL DATA), Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC) |
(35) CPSY |
14:20-14:40 |
Reliability Management in 2-layered Supervisor Processor |
Daiki Yamamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) |
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14:40-14:55 |
Break ( 15 min. ) |
Fri, Jan 30 PM 14:55 - 16:15 |
(36) RECONF |
14:55-15:15 |
Design and Implementation of Portable and High-speed FPGA Accelerator employing USB3.0 |
Takuma Usui, Ryohei Kobayashi, Kenji Kise (Tokyo Tech) |
(37) RECONF |
15:15-15:35 |
MieruSys Project : Developing an Advanced Computer System with Multiple FPGAs |
Yuki Matsuda, Eri Ogawa, Tomohiro Misono (Tokyo Tech), Naoki Fujieda, Shuichi Ichikawa (TUT), Kenji Kise (Tokyo Tech) |
(38) RECONF |
15:35-15:55 |
FPGA Vendor Independent Descriptions and Designs of Synchronous FIFOs |
Tomonori Izumi (Ritsumeikan Univ.) |
(39) RECONF |
15:55-16:15 |
Obfuscated Hardware Implementation of PLC Instructions with Opaque Predicates |
Kazuki Uyama, Naoki Fujieda, Shuichi Ichikawa (Toyohashi Tech.) |
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16:15-16:30 |
Break ( 15 min. ) |
Fri, Jan 30 PM 16:30 - 17:50 |
(40) CPSY |
16:30-16:50 |
A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor |
Keigo Mizotani, Yusuke Hatori, Yusuke Kumura, Masayoshi Takasu, Hiroyuki Chishiro, Nobuyuki Yamasaki (Keio Univ.) |
(41) CPSY |
16:50-17:10 |
A Latency-Aware Packet Scheduling on Responsive Link |
Kouhei Oosawa, Shuma Hagiwara, Yusuke Kumura, Keigo Mizotani, Masayoshi Takasu, Nobuyuki Yamasaki (Keio Univ.) |
(42) CPSY |
17:10-17:30 |
Real-time contour extraction for moving objects directly operating MPEG encoded data |
Syosuke Maruyama, Hidehiro Nakano, Arata Miyauchi (Tokyo City Univ.) |
(43) CPSY |
17:30-17:50 |
A Cache to Cache Communication Strategy for Wireless 3D Multi-Core Processors |
Masataka Matsumura (UEC), Masaaki Kondo (Univ. Tokyo), Hiroki Matsutani (Keio Univ.), Yasutaka Wada (Waseda Univ.), Hiroki Honda (UEC) |