Fri, Sep 10 AM AI Application 09:30 - 10:45 |
(1) |
09:30-09:55 |
A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA |
Ryosuke Kuramochi, Hiroki Nakahara (Tokyo Tech) |
(2) |
09:55-10:20 |
An FPGA Implementation of neural networks with multi-core structured using high level synthesis |
Akira Jinguji, Hiroki Nakahara (Tokyo Tech) |
(3) |
10:20-10:45 |
Convolutional neural network implementations using Vitis AI |
Akihiko Ushiroyama, Nobuya Watanabe, Akira Nagoya, Minoru Watanabe (Okayama Univ.) |
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10:45-11:00 |
Break ( 15 min. ) |
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11:00-12:45 |
Lunch break (RECONF Research Committee meeting will be held.) ( 105 min. ) |
Fri, Sep 10 PM 12:45 - 13:00 |
(4) |
12:45-13:00 |
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Fri, Sep 10 PM Invited Talk 13:00 - 13:50 |
(5) |
13:00-13:50 |
[Invited Talk]
Development of a very high-speed, low power computer system for Deep Learning at Preferred Networks |
Kei Hiraki (PFN) |
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13:50-14:10 |
Break ( 20 min. ) |
Fri, Sep 10 PM FPGA Application 1 14:10 - 15:25 |
(6) |
14:10-14:35 |
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(7) |
14:35-15:00 |
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(8) |
15:00-15:25 |
Parallel Calculation of Local Scores in Bayesian Network Structure Learning using FPGA |
Ryota Miyagi (Kyoto Univ.), Hideki Takase (U. Tokyo/JST) |
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15:25-15:45 |
Break ( 20 min. ) |
Fri, Sep 10 PM FPGA Application 2 15:45 - 16:35 |
(9) |
15:45-16:10 |
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(10) |
16:10-16:35 |
Multi-FPGA Based Hardware Acceleration for Genetic Data Analysis |
Imdad Ullah (Keio Univ.), Akram Ben Ahmed (AIST), Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.) |