Thu, Jul 17 AM 09:00 - 10:15 |
(1) |
09:00-09:25 |
Impact of the Different Nature of Interface Defect States on the NBTI and 1/f noise of High-k / Metal Gate pMOSFETs between (100) and (110) Crystal Orientations |
Motoyuki Sato, Yoshihiro Sugita, Takayuki Aoyama, Yasuo Nara, Yuzuru Ohji (Selete) |
(2) |
09:25-09:50 |
Drain Current Fluctuation in High-k Dielectric p-MOSFETs
-- Effects of Single-Hole Capture/Emission by the Traps in High-k Dielectric -- |
Shigeki Kobayashi, Masumi Saitoh, Ken Uchida (Corporate RDC, Toshiba Corp.) |
(3) |
09:50-10:15 |
Reduction of Vth Variation Utilizing HfSiOx for 45nm SRAM |
Gen Tsutsui, Kazuaki Tsunoda, Nayuta Kariya, Yutaka Akiyama, Tomohisa Abe, Shinya Maruyama, Tadashi Fukase, Mieko Suzuki, Yasushi Yamagata, Kiyotaka Imai (NECEL) |
|
10:15-10:30 |
Break ( 15 min. ) |
Thu, Jul 17 AM 10:30 - 12:10 |
(4) |
10:30-10:55 |
A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations |
Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka (Renesas Tech.), Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Katsuji Satomi, Hironori Akamatsu (Matsushita Elec.), Hirofumi Shinohara (Renesas Tech.) |
(5) |
10:55-11:20 |
A small-delay defect detection technique for dependable LSIs |
Koichiro Noguchi, Koichi Nose (NEC), Toshinobu Ono (NECEL), Masayuki Mizuno (NEC) |
(6) |
11:20-12:10 |
[Invited Talk]
Progress of compact model for CMOS circuit design
-- Performance of HiSIM model based on the surface potential model -- |
Tatsuya Ohguro (Hiroshima Univ./Toshiba), Mitiko Miura-Mattausch (Hiroshima Univ.) |
|
12:10-13:10 |
Lunch ( 60 min. ) |
Thu, Jul 17 PM 13:10 - 14:50 |
(7) |
13:10-14:00 |
[Invited Talk]
Super Chip Technology to Achieve Ultimate Integration |
Mitsumasa Koyanagi, Tetsu Tanaka (Tohoku Univ.) |
(8) |
14:00-14:50 |
[Special Talk]
Present Status and Future Trend of Characteristic Variations in Scaled CMOS |
Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete), Kiyoshi Takeuchi, Takaaki Tsunomura (/MIRAI-Selete), Arifin T.Putra (Univ. of Tokyo), Akio Nishida, Shiro Kamohara (/MIRAI-Selete) |
|
14:50-15:05 |
Break ( 15 min. ) |
Thu, Jul 17 PM 15:05 - 16:20 |
(9) |
15:05-15:30 |
A Fully Logic-Process-Compatible, SESO-memory Cell with 0.1-FIT/Mb Soft Error, 100-MHz Random Cycle, and 100-ms Retention |
Norifumi Kameshiro, Takao Watanabe, Tomoyuki Ishii, Toshiyuki Mine (Hitachi, Ltd.), Toshiaki Sano (Renesas), Hidefumi Ibe, Satoru Akiyama (Hitachi, Ltd.), Kazumasa Yanagisawa, Takashi Ipposhi, Toshiaki Iwamatsu, Yasuhiko Takahashi (Renesas) |
(10) |
15:30-15:55 |
New design technology of Independent-Gate controlled Stacked type 3D transistor for system LSI |
Yu Hiroshima, Shigeyoshi Watanabe (SIT) |
(11) |
15:55-16:20 |
Co-design of CNT based devices and circuitry
-- How can CNT-based circuit overcome Si-CMOS? -- |
Shinobu Fujita (Toshiba RDC) |
|
16:20-16:35 |
Break ( 15 min. ) |
Thu, Jul 17 PM 16:35 - 17:35 |
(12) |
16:35-17:35 |
[Panel Discussion]
Future prospects on new device and circuit technologies (1)
Tatsuya Ohguro (Hiroshima Univ. and Toshiba), Mitsumasa Koyanagi (Tohoku Univ.), Toshiro Hiramoto (Univ. Tokyo) |
Fri, Jul 18 AM 09:00 - 10:15 |
(13) |
09:00-09:25 |
Study of high-Speed low-power system LSI for sub-threshold operation |
Makoto Tsurukubo, Shigeyoshi Watanabe (SIT) |
(14) |
09:25-09:50 |
Examination of Low-power system LSI architecture by Real time scheduling |
Yoshikazu Sato, Shigeyoshi Watanabe (SIT) |
(15) |
09:50-10:15 |
A Sub-μs Wake-up Time Power Gating Technique with Bypass Power Line for Rush Current Support |
Koichi Nakayama, Ken-ichi Kawasaki, Tetsuyoshi Shiota, Atsuki Inoue (Fujitsu Lab.) |
|
10:15-10:30 |
Break ( 15 min. ) |
Fri, Jul 18 AM 10:30 - 12:10 |
(16) |
10:30-11:20 |
[Invited Talk]
CMOS-based biomedical photonic devices |
Takashi Tokuda, Jun Ohta (NAIST) |
(17) |
11:20-12:10 |
[Invited Talk]
Problems and Prospect of 3D Integration using Wireless and Optical Interconnection Technologies |
Atsushi Iwata, Shin Yokoyama (Hiroshima Univ.) |
|
12:10-13:10 |
Lunch ( 60 min. ) |
Fri, Jul 18 PM 13:10 - 14:00 |
(18) |
13:10-14:00 |
[Invited Talk]
RF MEMS for Reconfigurable CMOS Radio |
Kazuya Masu (Tokyo Tech.) |
|
14:00-14:15 |
Break ( 15 min. ) |
Fri, Jul 18 PM 14:15 - 15:55 |
(19) |
14:15-14:40 |
Realistic future trend of non-voltile semiconductor memory and feasibility study of ultra-low-cost high-speed universal non-volatile memory
-- feasibility study of BiCS type FeRAM and MRAM -- |
Shigeyoshi Watanabe, Koichi Sugano, Shouto Tamai (Shonan Institute of Tech.) |
(20) |
14:40-15:05 |
Fabrication of Ultra Shallow Junction and Improvement of Metal Gate High-k CMOS Performance by FSP-FLA (Flexibly-Shaped-Pulse Flash-Lamp-Annealing) Technology |
Takashi Onizawa, Shinichi Kato, Takayuki Aoyama, Yasuo Nara, Yuzuru Ohji (selete) |
(21) |
15:05-15:30 |
Impact of Tantalum Composition in TaCx/HfSiON Gate Stack on Device Performance of Aggressively Scaled CMOS Devices with SMT and Strained CESL |
Masakazu Goto, Kosuke Tatsumura, Shigeru Kawanaka, Kazuaki Nakajima, Reika Ichihara, Yasuhito Yoshimizu, Hiroyuki Onoda, Koji Nagatomo, Toshiyuki Sasaki, Takashi Fukushima, Akiko Nomachi, Seiji Inumiya, Tomonori Aoyama, Masato Koyama, Yoshiaki Toyoshima (Toshiba Corp.) |
(22) |
15:30-15:55 |
High Performance Sub-35 nm Bulk CMOS with Hybrid Gate Structures of NMOS; Dopant Confinement Layer (DCL) / PMOS; Ni-FUSI by Using Flash Lamp Anneal (FLA) in Ni-Silicidation
-- Hybrid Gate Structures -- |
Hiroyuki Ohta (Fujitsu Lab.), Kazuo Kawamura (FML), Hidenobu Fukutome (Fujitsu Lab.), Mitsugu Tajima, Ken-ichi Okabe (FML), Keiji Ikeda, Kimihiko Hosaka, Yoichi Momiyama, Shigeo Satoh, Toshihiro Sugii (Fujitsu Lab.) |
|
15:55-16:10 |
Break ( 15 min. ) |
Fri, Jul 18 PM 16:10 - 17:10 |
(23) |
16:10-17:10 |
[Panel Discussion]
Future prospects on new device and circuit technologies (2)
Takashi Tokuda (NAIST), Atsushi Iwata (Hiroshima Univ.), Kazuya Masu (Tokyo Tech.) |