Wed, Mar 1 AM VLD 11:00 - 13:25 |
(1) |
11:00-11:25 |
Measured Evaluation of BTI Degradation in a 65nm FDSOI Process using Ring Oscillators with Same Circuit Structure |
Daisuke Kikuta (KIT), Ryo Kishida (TPU), Kazutoshi Kobayashi (KIT) |
(2) |
11:25-11:50 |
Pass/Fail Threshold Determination Based on Gaussian Process Regression in LSI Test |
Daisuke Goeda (KIT), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (SCK), Michihiro Shintani (KIT) |
(3) |
11:50-12:15 |
Acceleration of Memristor Modeling Based on Machine Learning Using Gaussian Process |
Yuta Shintani, Michiko Inoue (Naist), Michihiro Shintani (Kyoto Institute of Technology) |
|
12:15-13:25 |
Break ( 70 min. ) |
Wed, Mar 1 PM VLD 13:25 - 14:55 |
(4) |
13:25-13:50 |
Programmable Binary Hyperdimensional Computing Accelerator for Low Power Devices |
Yuya Isaka (NAIST), Nau Sakaguchi (SJSU), Michiko Inoue (NAIST), Michihiro Shintani (KIT) |
(5) |
13:50-14:15 |
Circuit Optimization and Simulation Evaluation for Ultra-Low Voltage of LRPUF Using Manufacturing Variability of Leakage Current |
Shunkichi Hata, Kimiyoshi Usami (SIT) |
(6) |
14:15-14:40 |
A Study on Interface Circuits for Burst Transfers from Synchronous to Asynchronous Circuits |
Shogo Semba, Hiroshi Saito (UoA) |
|
14:40-14:55 |
Break ( 15 min. ) |
Wed, Mar 1 PM VLD 14:55 - 16:25 |
(7) |
14:55-15:20 |
High fidelity mask pattern generation method by amplitude component evaluation |
Yu Horimoto, Sota Saito, Atsushi Takahashi (Tokyo Tech), Yukihide Kohira (Univ. of Aizu), Chikaaki Kodama (KIOXIA) |
(8) |
15:20-15:45 |
A fast SRAF optimization using Voronoi diagram and LUT based intensity evaluation |
Sota Saito, Yu Horimoto, Atsushi Takahashi (Tokyo Tech), Yukihide Kohira (Univ. of Aizu), Chikaaki Kodama (KIOXIA) |
(9) |
15:45-16:10 |
A Feature Vector Considering Characteristics of Optical System for Lithography Hotspot Detection |
Masahiro Yamamoto, Masato Inagi, Shinobu Nagayama (HCU) |
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16:10-16:25 |
Break ( 15 min. ) |
Wed, Mar 1 PM VLD 16:25 - 17:40 |
(10) |
16:25-16:50 |
Large-scale SAT Solution Search by FPGA Implementation of Attraction-Repulsion Control-Type Amoeba Algorithm |
Hideharu Amano, Torao Okuyama (Keio Univ.), Kaori Okoda, Masashi Aono (Amoeba Energy) |
(11) |
16:50-17:15 |
A Deep Reinforcement Learning-based Routing Algorithm for Unknown Erroneous Cells in DMFBs |
Tomohisa Kawakami, Chiharu Shiro (Ritsumeikan Univ.), Hiroki Nishikawa (Osaka Univ.), Kong Xiangbo, Hiroyuki Tomiyama, Shigeru Yamashita (Ritsumeikan Univ.) |
(12) |
17:15-17:40 |
Routing with washing droplets in MEDA biochips |
Shiro Chiharu (Ritsumei), Nishikawa hiroki (Osaka), Xiangbo Kong, Tomiyama Hiroyuki, Yamashita Shigeru (Ritsumei) |
Thu, Mar 2 AM VLD 09:30 - 11:00 |
(13) |
09:30-09:55 |
|
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(14) |
09:55-10:20 |
Implementation of power-outage tolerant VLSI system using asynchronous circuits |
Masashi Imai (Hirosaki Univ.) |
(15) |
10:20-10:45 |
A Study and an Evaluation of the High Performance Deep Neural Network Inference circuit on FPGAs |
Ryo Yamamoto, Kenya Sugihara, Yoshihiro Ogawa (Mitsubishi Electric) |
|
10:45-11:00 |
Break ( 15 min. ) |
Thu, Mar 2 AM VLD 11:00 - 13:25 |
(16) |
11:00-11:25 |
|
|
(17) |
11:25-11:50 |
Skew Tunability Aware High Level Synthesis Considering Resource Binding-Driven Thermal Distribution |
Mineo Kaneko (JAIST) |
(18) |
11:50-12:15 |
Automatic Synthesis of Decoupled Data Orchestration in High-Level Synthesis |
Masayuki Usui, Shinya Takamaeda (UTokyo) |
|
12:15-13:25 |
Break ( 70 min. ) |
Thu, Mar 2 PM VLD 13:25 - 15:20 |
(19) |
13:25-13:50 |
[Memorial Lecture]
Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects |
Takuma Nagao (NAIST), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (Sony Semiconductor Manufacturing), Michiko Inoue (NAIST), Michihiro Shintani (Kyoto Institute of Technology) |
(20) |
13:50-14:15 |
[Memorial Lecture]
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology |
Chenlin Shi, Shinobu Miwa (UEC), Tongxin Yang, Ryota Shioya (UOT), Hayato Yamaki, Hiroki Honda (UEC) |
(21) |
14:15-14:40 |
[Memorial Lecture]
DependableHD: A Hyperdimensional Learning Framework for Edge-oriented Voltage-scaled Circuits [Memorial lecture] |
Dehua Liang (Osaka Univ.), Hiromitsu Awano (Kyoto Univ.), Noriyuki Miura, Jun Shiomi (Osaka Univ.) |
(22) |
14:40-15:05 |
[Memorial Lecture]
A method for synthesizing quantum circuits satisfying NNA constraints using SMT solvers |
Kyehei Seino, Shigeru Yamashita (Ritsumeikan University) |
|
15:05-15:20 |
Break ( 15 min. ) |
Thu, Mar 2 PM HWS 15:20 - 16:25 |
(23) |
15:20-15:45 |
Secure Cache System against On-Chip Threats |
Keisuke Kamahori, Shinya Takamaeda (UTokyo) |
(24) |
15:45-16:10 |
Hiding Memory Structure for IP Protection |
Sun Tanaka, Shinya Takamaeda (UTokyo) |
|
16:10-16:25 |
Break ( 15 min. ) |
Thu, Mar 2 PM VLD 16:25 - 17:40 |
(25) |
16:25-16:50 |
Multiple Constant Convolution with Minimum Number of Full Adders. |
Kota Kuga, Shinya Takamaeda (UTokyo) |
(26) |
16:50-17:15 |
Reducing Conflict Misses with Multiple Indexings in Compressed Caches |
Tasuku Fukami, Shinya Takamaeda (UTokyo) |
(27) |
17:15-17:40 |
Communication-Efficient Federated Learning with Gradient Boosting Decision Trees |
Kotaro Shimamura, Shinya Takamaeda (UTokyo) |
Fri, Mar 3 AM VLD 09:30 - 10:45 |
(28) |
09:30-09:55 |
Global routing method imitating car path search |
Yusuke Yamaguchi, Kunihiro Fujiyoshi (TUAT) |
(29) |
09:55-10:20 |
Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing |
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (Jedat) |
(30) |
10:20-10:45 |
Pair Symmetrical Routing in Common Centroid Placement with Common Signal Constraints |
Zuan Jo, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (JEDAT) |
|
10:45-11:00 |
Break ( 15 min. ) |
Fri, Mar 3 AM VLD 11:00 - 12:15 |
(31) |
11:00-11:25 |
|
Yusei Yano, Shinji Nozaki, Tomohide Aizawa, Yukihide Kohira (Univ. of Aizu) |
(32) |
11:25-11:50 |
Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits |
Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara (Nagoya Univ.) |
(33) |
11:50-12:15 |
A Seed Selection Method to Minimize Test Application Time for Logic BIST Using Pseudo Boolean Optimization |
Rei Miura, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) |
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12:15-13:25 |
Break ( 70 min. ) |
Fri, Mar 3 PM VLD 13:25 - 15:20 |
(34) |
13:25-13:50 |
High-Performance and Programmer-Friendly Secure Non-Volatile Memory using Temporal Memory-Access Redirection |
Ryo Koike, Shinya Takamaeda (UTokyo) |
(35) |
13:50-14:15 |
A Logic Locking Method based on Function Modification Circuit |
Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Rei Miura, Toshinori Hosokawa (Nihon Univ.) |
(36) |
14:15-14:40 |
N/A |
Yuka Ikegami, Kazuki Yamashita (Waseda Univ.), Kento Hasegawa, Kazuhide Fukushima, Shinsaku Kiyomoto (KDDI Research, Inc.), Nozomu Togawa (Waseda Univ.) |
(37) |
14:40-15:05 |
Toggle-based simulation of side-channel attack against multiplier for pairing-based cryptography |
Saito Kikuoka, Makoto Ikeda (Tokyo Univ.) |
|
15:05-15:20 |
Break ( 15 min. ) |
Fri, Mar 3 PM HWS 15:20 - 16:25 |
(38) |
15:20-15:45 |
Design optimization of TFHE-based 4+ input homomorphic logic gates by error controlling |
Yinfan Zhao, Makoto Ikeda (Tokyo Univ.) |
(39) |
15:45-16:10 |
Study of Intrinsic ID extracted from RG-DTM Arbiter PUF implemented on FPGA |
Mika Sakai, Tatsuya Oyama, Kota Yoshida (Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.) |
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16:10-16:25 |
Break ( 15 min. ) |
Fri, Mar 3 PM VLD 16:25 - 17:40 |
(40) |
16:25-16:50 |
NA |
Ryusei Eda, Kota Hisafuru, Ryotaro Negishi, Nozomu Togawa (Waseda Univ.) |
(41) |
16:50-17:15 |
NA |
Hibiki Nakanishi, Kota Hisafuru, Ryotaro Negishi, Nozomu Togawa (Waseda Univ.) |
(42) |
17:15-17:40 |
NA |
Takuma Yabe, Kota Hisafuru, Ryotaro Negishi, Nozomu Togawa (Waseda Univ.) |
Sat, Mar 4 AM HWS 10:00 - 11:05 |
(43) |
10:00-10:25 |
Importance of Inverters Placement in Ring-Oscilator for Laser Irradiation Detection |
Shungo Hayashi (YNU), Junichi Sakamoto (AIST/YNU), Masaki Chikano, Tsutomu Matsumoto (YNU) |
(44) |
10:25-10:50 |
Fundamental study of distance spoofing attack against dToF lidar with interference mitigation function |
Midori Tomijima, Daisuke Fujimoto, Yuichi Hayashi (NAIST) |
|
10:50-11:05 |
Break ( 15 min. ) |
Sat, Mar 4 AM HWS 11:05 - 13:30 |
(45) |
11:05-11:30 |
Clone Resistance of Artifact Metrics: Scanning Probe Lithography Based Clones |
Naoki Yoshida, Akira Iwahashi (YNU), Hoga Morihisa, Junko Ohta, Kaoru Sumiya (AIST), Tsutomu Matsumoto (YNU) |
(46) |
11:30-11:55 |
Clone Resistance of Artifact Metrics Systems Based on White Light Interferometry and Phase Only Correlation |
Akira Iwahashi, Naoki Yoshida, Tsutomu Matsumoto (YNU) |
(47) |
11:55-12:20 |
Cloud Based Evaluation of Communication Bandwidth and Tracking Time of Traceable Aggregate Signature Protocols |
Koudai Aoyama, Riku Anzai, Junichi Sakamoto, Naoki Yoshida, Tsutomu Matsumoto (Yokohama National Univ.) |
|
12:20-13:30 |
Break ( 70 min. ) |
Sat, Mar 4 PM HWS 13:30 - 14:45 |
(48) |
13:30-13:55 |
Threat of EM Information Leakage from Speakerphones Due to IEMI and Suppression Indexes for EMC Countermeasures |
Seiya Takano, Yuichi Hayashi (NAIST) |
(49) |
13:55-14:20 |
* |
Masaru Mashiba, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuzi Miki, Nagata Makoto (Kobe Univ.) |
(50) |
14:20-14:45 |
Side-channel Information Leakage Resistance Evaluation of Cryptographic Multi- chip Modules |
Takumi Matsumaru, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuzi Miki, Makoto Nagata (Kobe Univ.) |