Wed, Feb 28 AM
09:30 - 10:45 |
(1)
VLD |
09:30-09:55 |
On Fast Computation of RBF Approximate Function by FPGA Implementation |
Shogo Masuda, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
(2)
VLD |
09:55-10:20 |
On Memory Size Reduction of Programmable Hardware for Random Forest based Network Intrusion Detection |
Binbin Xue, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
(3)
VLD |
10:20-10:45 |
k-Nearest Neighbor Search Hardware Using Locality Sensitive Hashing for High-Dimensional Data |
Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.) |
| |
10:45-11:00 |
Break ( 15 min. ) |
Wed, Feb 28 AM
11:00 - 12:15 |
(4)
VLD |
11:00-11:25 |
A fast routing method for multi-terminal nets using constraint satisfaction problem |
Saki Yamaguchi, Yasuhiro Takashima (Univ. of Kitakyushu) |
(5)
VLD |
11:25-11:50 |
Amoeba-inspired SAT Solvers on FPGA through High Level Synthesis |
Hoang Ngoc Anh Nguyen (Tokyo Tech), Masashi Aono (Keio Univ.), Yuko Hara-Azumi (Tokyo Tech) |
(6)
VLD |
11:50-12:15 |
Systematic Analysis Framework of Variables Significance towards Approximate Computing |
Sara Ayman Metwalli, Yuko Hara-Azumi (Tokyo Tech) |
| |
12:15-13:30 |
Lunch Break ( 75 min. ) |
Wed, Feb 28 PM
13:30 - 14:45 |
(7)
VLD |
13:30-13:55 |
Random Testing of Android Virtual Machine by Valid Dex File Generation |
Hirofumi Ikeo, Ryotaro Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ.) |
(8)
VLD |
13:55-14:20 |
Congestion Aware High Level Synthesis Design Flow with Source Compiler |
Masato Tatsuoka, Mineo Kaneko (JAIST) |
(9)
VLD |
14:20-14:45 |
Development of Loop Flattening Tool that Reduces Cycle Overhead in Loop Pipelining of Nested Loops in High Level Synthesis |
Daisuke Ishikawa, Kenshu Seto (TCU) |
| |
14:45-15:00 |
Break ( 15 min. ) |
Wed, Feb 28 PM
15:00 - 16:15 |
(10)
VLD |
15:00-15:25 |
A Study on Quality Improvement of Frame Interpolation Method with High-Resolution and High-Frame Rate Video Using Foreground Elimination and Contour Extraction |
Hirofumi Ihara, Takashi Imagawa (Ritumeikan Univ), Hiroki Uesaka, Shingo Kokami, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ), Hiroyuki Ochi (Ritumeikan Univ) |
(11)
VLD |
15:25-15:50 |
Architecture of Full-HD 60-fps Real-time Optical Flow Processor |
Satoshi Kanda (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) |
(12)
VLD |
15:50-16:15 |
A Study of Acceleration Optimization for an EV Cart with a Lithium-ion Battery |
Haruya Fujii, Yoshiki Tsuchida, Tomoki Abe, Lei Lin, Masahiro Fukui (Ritsumeikan Univ.) |
| |
16:15-16:30 |
Break ( 15 min. ) |
Wed, Feb 28 PM
16:30 - 18:10 |
(13)
VLD |
16:30-16:55 |
Reconfiguration for Fault Tolerant FPGA Considering Incremental Multiple Faults |
Cheng Ma, Mineo Kaneko (JAIST) |
(14)
VLD |
16:55-17:20 |
Reliability Evaluation of Mixed Error Correction Scheme for Soft-Error Tolerant Datapaths |
Junghoon Oh, Mineo Kaneko (JAIST) |
(15)
VLD |
17:20-17:45 |
Evaluation of a Radiation-Hardened Method and Soft Error Resilience on Stacked Transistors in 28/65 nm FDSOI Processes |
Haruki Maruoka, Kodai Yamada, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi (KIT) |
(16)
VLD |
17:45-18:10 |
Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage |
Mitsunori Ebara, Haruki Maruoka, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) |
Thu, Mar 1 AM
09:00 - 10:15 |
(17)
VLD |
09:00-09:25 |
A Study of Lithography Hotspot Detection Method Based on Feature Vectors Considering Distances between Wires |
Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
(18)
VLD |
09:25-09:50 |
Efficient Generation of Lithography Hotspot Detector based on Transfer Learning |
Shuhei Suzuki, Yoichi Tomioka (UoA) |
(19)
VLD |
09:50-10:15 |
Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning |
Kota Muroi, Yukihide Kohira (Univ. of Aizu) |
| |
10:15-10:30 |
Break ( 15 min. ) |
Thu, Mar 1 AM
10:30 - 11:45 |
(20)
VLD |
10:30-10:55 |
A Motif Extraction Method Using Monte-Carlo Tree Search and its Experimental Evaluation |
Yusuke Yuasa, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
(21)
VLD |
10:55-11:20 |
Implementation and Evaluation of MCTS-Based Parallel Prefix Adder Synthesis |
Taeko Matsunaga (NBU), Yusuke Matsunaga (Kyushu Univ.) |
(22)
VLD |
11:20-11:45 |
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|
| |
11:45-13:00 |
Lunch Break ( 75 min. ) |
Thu, Mar 1 PM
13:00 - 14:15 |
(23)
VLD |
13:00-13:25 |
An Evaluation of Graph Reduction Technique for Delay Insertion of General-Synchronous Circuit |
Yuki Arai, Shuji Tsukiyama (Chuo Univ.) |
(24)
VLD |
13:25-13:50 |
A Study on Energy Optimization for Asynchronous RTL Models with Bundled-data Implementation |
Shogo Semba, Hiroshi Saito (UoA) |
(25)
VLD |
13:50-14:15 |
Evaluating logic encryption methods using error correcting logic synthesis |
Yusuke Matsunaga (Kyushu Univ.) |
| |
14:15-14:30 |
Break ( 15 min. ) |
Thu, Mar 1 PM
14:30 - 15:45 |
(26)
VLD |
14:30-14:55 |
A SW/HW Partitioning for Model Based Design
-- A automated SW/HW partitioning using Matlab/Simulink and C based High Level Synthesis -- |
Ryo Yamamoto, Koki Murano, Ayumu Yamamoto, Yoshihiro Ogawa (Mitsubishi Electric) |
(27)
VLD |
14:55-15:20 |
Core allocation with mixed multirate tasks in model-based parallelization |
Yoshihiro Ikeda, Masato Edahiro (Nagoya Univ) |
(28)
VLD |
15:20-15:45 |
Hardware/Software co-design environment in model-based parallelization (MBP) |
Kazuki Kashiwabara, Shinya Honda, Masato Edahiro (Nagoya Univ.) |
| |
15:45-16:00 |
Break ( 15 min. ) |
Thu, Mar 1 PM
16:00 - 17:15 |
(29)
VLD |
16:00-16:25 |
A C Description Approach for High Level Synthesis to Configure DNN Inference Circuit |
Takuya Okamoto, Ryota Yamamoto, Shinya Honda (Nagoya Univ.) |
(30)
VLD |
16:25-16:50 |
A Concept of DNN Framework for Embedded System Using FPGA |
Ryota Yamamoto, Takuya Okamoto, Shinya Honda (Nagoya Univ.), Qian Zhao, Toki Matsumoto, Yukikazu Nakamoto (Hyogo Univ.), Tamotsu Sakai, Tetsuya Aoyama, Kazutoshi Wakabayashi (NEC) |
(31)
VLD |
16:50-17:15 |
Impedance Evaluation Mechanism with Automatic Calibration based on Automatic Balanced Bridge |
Takaaki Shirakawa, Sakai Ryosuke, Nakatake Shigetoshi (Univ. of Kitakyusyu) |
| |
18:30-21:30 |
Banquet ( 180 min. ) |
Fri, Mar 2 AM
09:00 - 10:15 |
(32)
VLD |
09:00-09:25 |
On-chip and ultra low current measurement circuit based on potentiostat method |
Daishi Isogai, Takaaki Shirakawa, Shigetoshi Nakatake (Univ. of Kitakyushu) |
(33)
VLD |
09:25-09:50 |
A study on interconnect delay computation for via-switch based FPGA |
Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto (Osaka Univ.) |
(34)
VLD |
09:50-10:15 |
Approximate computing based on extension of DRAM refresh interval and data correction |
Takamasa Fukasawa, Kimiyoshi Usami (SIT) |
| |
10:15-10:30 |
Break ( 15 min. ) |
Fri, Mar 2 AM
10:30 - 11:45 |
(35)
VLD |
10:30-10:55 |
Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data |
Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Hideharu Amano, Takeharu Ikezoe (Keio Univ.), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) |
(36)
VLD |
10:55-11:20 |
Experimental study on power reduction by approximate computing with voltage over-scaling |
Masahiro Sato, Yutaka Masuda, Masanori Hashimoto (Osaka Univ.) |
(37)
VLD |
11:20-11:45 |
Energy Reduction of Standard-Cell Memory Exploiting Selective Activation |
Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) |
| |
11:45-13:00 |
Lunch Break ( 75 min. ) |
Fri, Mar 2 PM
13:00 - 13:50 |
| (38) |
13:00-13:50 |
[Invited Talk]
Cyber attacks and countermeasures for smart factories in the Age of Industry 4.0 |
Takeshi Yoneda (Mitsubishi Electric Corp.) |
| |
13:50-14:05 |
Break ( 15 min. ) |
Fri, Mar 2 PM
14:05 - 15:20 |
| (39) |
14:05-14:30 |
PL-PUF Implementation by Improvement of Capturing Timing Control Circuit |
Yasuhiro Ogasahara, Yohei Hori, Hanpei Koike (AIST) |
| (40) |
14:30-14:55 |
Modeling Attacks on Double-Arbiter PUF Using Deep Neural Network |
Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda (UTokyo) |
| (41) |
14:55-15:20 |
Machine Learning Attack Using Selectable Challenge Set for Feed-Forward PUF |
Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) |
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