IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   Prev VLD Conf / Next VLD Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Shigetoshi Nakatake (Univ. of Kitakyushu)
Vice Chair Yuichi Sakurai (Hitachi)
Secretary Yukihiro Sasagawa (Socionext), Masashi Imai (Hirosaki Univ.)
Assistant Takuma Nishimoto (Hitachi)

Technical Committee on Circuits and Systems (CAS) [schedule] [select]
Chair Yasutoshi Aibara (OmniVision)
Vice Chair Norihiko Shinomiya (Soka Univ.)
Secretary Daisuke Kasamatsu (Soka Univ.), Hiroto Suzuki (Renesas Electronics)
Assistant Nao Ito (NIT, Toyama college), Motoi Yamaguchi (TECHNOPRO), Shinji Shimoda (Sony Semiconductor Solutions), Shunsuke Koshita (Hachinohe Inst. of Tech.)

Technical Committee on Signal Processing (SIP) [schedule] [select]
Chair Takayuki Nakachi (Ryukyu Univ.)
Vice Chair Koichi Ichige (Yokohama National Univ.), Kiyoshi Nishikawa (okyo Metropolitan Univ.)
Secretary Shoko Imaizumi (Chiba Univ.), Seisuke Kyochi (Kogakuin Univ.)
Assistant Taichi Yoshida (UEC), Sayaka Shiota (Tokyo Metropolitan Univ.)

Technical Committee on Mathematical Systems Science and its Applications (MSS) [schedule] [select]
Chair Shingo Yamaguchi (Yamaguchi Univ.)
Vice Chair Toshiyuki Miyamoto (Osaka Inst. of Tech.)
Secretary Naoki Hayashi (Osaka Univ.), Jianquan Liui (NEC)
Assistant Masato Shirai (Shimane Univ.)

Conference Date Thu, Jul 6, 2023 09:30 - 17:50
Fri, Jul 7, 2023 09:30 - 16:00
Topics  
Conference Place  
Sponsors This conference is co-sponsored by IEEE Signal Processing Society Tokyo Joint Chapter. This conference is technical co-sponsored by IEEE Circuits and Systems Society Japan Chapter(IEEE CASS JC), IEEE Signal Processing Society Tokyo Joint Chapter and APSIPA Japan Chapter.
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on MSS, CAS, SIP, VLD.

Thu, Jul 6 AM  CAS1
09:30 - 10:30
(1) 09:30-09:50 Performance Improvement by Integrating Former and Latter Processes of Pencil Drawing Style Image Conversion on High-Level Synthesized Hardware. Honoka Tani, Akira Yamawaki (Kyutech)
(2) 09:50-10:10 Hardware Development of Edge-Preserving Bubble Image Conversion in High-level Synthesis Qin Jiang, Yamawaki Akira (Kyutech)
(3) 10:10-10:30 Performance Improvement by Memory access and Process-level Pipelining for High-level Synthesized Sprite Drawing Hardware Yuka Otani, Akira Yamawaki (Kyutech)
  10:30-10:40 Break ( 10 min. )
Thu, Jul 6 AM  VLD1
10:40 - 11:40
(4) 10:40-11:00 Autoencoder Based Incremental LSI Test Escape Detection Using Transfer Learning Ayano Takaya, Michihiro Shintani (KIT)
(5) 11:00-11:20 Lifetime improvement of Memristor-based Hyperdimensional Computing Inference Accelerator by Error Detection and Built-in Self Repair Tetsuro Iwasaki, Michihiro Shintani (KIT)
(6) 11:20-11:40 Fast Method of Integer Linear Programming for Set-Pair Routing Problem Yasuhiro Takashima (Univ. of Kitakyushu)
  11:40-13:00 Break ( 80 min. )
Thu, Jul 6 PM  Panel Discussion
13:00 - 14:30
(7) 13:00-14:30 [Panel Discussion]
Democratization of Researches in Circuits and Systems fields and Initiatives in Technical Groups
Makoto Ikeda (The Univ. of Tokyo), Yasutoshi Aibara (OVT), Shigetoshi Nakatake (The Univ. of Kitakyushu), Takayuki Nakachi (Univ. of Ryukyus), Shingo Yamaguchi (Yamaguchi Univ.)
  14:30-14:40 Break ( 10 min. )
Thu, Jul 6 PM  SIP
14:40 - 15:40
(8) 14:40-15:00 Convergence Acceleration of Particle-based Variational Inference by Deep Unfolding Yuya Kawamura, Satoshi Takabe (Tokyo Tech)
(9) 15:00-15:20 Baby monitoring system using Magnification and Optical flow Kazutaka Kikuta, Ken. T. Murata (NICT)
(10) 15:20-15:40 A Study on Golomb Coding for Scrambled Domain Layered Coding Compatible with JPEG XS Takayuki Nakachi (Univ. of the Ryukyus), Hiroyuki Kimiyama (Daido), Mitsuru Murayama (KAIST)
  15:40-15:50 Break ( 10 min. )
Thu, Jul 6 PM  CAS2
15:50 - 16:50
(11) 15:50-16:10 Effects of Parasitic Elements on LC/CL Matching Circuits Satoshi Tanaka, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.)
(12) 16:10-16:30 Research on income inequality using Lengnick economic model Tessei Morisawa, Shima Takagi, Nao Ito (NIT.Toyama College)
(13) 16:30-16:50 Band-combined broadband amplification system with preequalization Yuudai Nishi, Yohtaro Umeda, Kyoya Takano (Tokyo Univ. of Science)
  16:50-17:00 Break ( 10 min. )
Thu, Jul 6 PM  Invited Talk (CAS)
17:00 - 17:50
(14) 17:00-17:50 [Invited Talk]
Introduction of NanoVNA
-- Open Source Handheld Verctor Network Analyzer --
Tomohiro Takahashi (CM)
Fri, Jul 7 AM  MSS
09:30 - 11:10
(15) 09:30-09:50 Proposal and Evaluation of Distributed Formation Method based on a Cyclic Pursuit Strategy Anna Fujioka, Masaki Ogura, Naoki Wakamiya (Osaka Univ.)
(16) 09:50-10:10 Finite-Time Control of Boolean Networks Considering Specifications on Control Inputs Fuma Motoyama, Koichi Kobayashi, Yuh Yamashita (Hokkaido Univ.)
(17) 10:10-10:30 Notion of Current-State Opacity and Its Verification for Discrete-Time Piecewise Linear Systems Taiga Matsumae, Koichi Kobayashi, Yuh Yamashita (Hokkaido Univ.)
(18) 10:30-10:50 A greedy stable time via various 2-hop trees in wireless sensor networks Yoshihiro Kaneko (Gifu Univ.)
(19) 10:50-11:10 Population-Game-Based Distributed Allocation Method of Dynamic Coverage and Target Tracking Tasks for Mobile Sensor Networks Takafumi Kanazawa (Setsunan Univ.)
  11:10-11:20 Break ( 10 min. )
Fri, Jul 7 AM  CAS3
11:20 - 12:20
(20) 11:20-11:40 Enhancing Glycan Recognition Pattern Learning with Tree-Structured Data Mining Kento Totsuka, Norihiko Shinomiya, Kiyoko Kinoshita, Masae Hosoda (Soka Univ.)
(21) 11:40-12:00 The joint of unequal clustering routings EECS and EEUC in wireless sensor networks
-- The impact of parameters --
Yoshihiro Kaneko, Kohei Kawabata (Gifu Univ.)
(22) 12:00-12:20 Polygon Fracturing Method Considering Maximum Size Limit Taiki Matsuzaki, Kunihiro Fujiyoshi (TUAT)
  12:20-13:30 Break ( 70 min. )
Fri, Jul 7 PM  VLD2
13:30 - 14:50
(23) 13:30-13:50
(24) 13:50-14:10
(25) 14:10-14:30
(26) 14:30-14:50
  14:50-15:00 Break ( 10 min. )
Fri, Jul 7 PM  CAS4
15:00 - 16:00
(27) 15:00-15:20 ADC analog Filtering dependence of signal transmission characteristics of ADC bandwidth doubler with analog/digital hybrid equivalent ideal filter Koki Ihara, Yuya Fujiwara, Yohtaro Umeda, Kyoya Takano (Tokyo Univ. of science)
(28) 15:20-15:40 Verification of effectiveness of the greedy algorithm for the influence maximization problem focusing on the authenticity in OSN Jodai Yoshiue, Atsushi Wakamatsu, Masaaki Miyasita, Norihiko Shinomiya (Soka Univ.)
(29) 15:40-16:00 Study for analyzing theta waves more clinically using the Fujimori method Mitsuki Miyazoe (TUS), Takashi Yoshida (TMCIT), Mitsuo Hayashi (Hiroshima Univ.), Naoyuki Aikawa (TUS)
  16:00-16:10 Break ( 10 min. )
  16:10-16:30 ( 20 min. )

Announcement for Speakers
General TalkEach speech will have 15 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Masashi IMAI (Hirosaki Univ. )
E--mail: bi-u 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
CAS Technical Committee on Circuits and Systems (CAS)   [Latest Schedule]
Contact Address CAS administrator Group
E--mail: cas-adn 
SIP Technical Committee on Signal Processing (SIP)   [Latest Schedule]
Contact Address IEICE Technical Group on Signal Processing
Email: sip-n 
MSS Technical Committee on Mathematical Systems Science and its Applications (MSS)   [Latest Schedule]
Contact Address Koichi Kobayashi (Hokkaido University)
Tel: +81-11-706-6452
E--mail: k-bassiisti 


Last modified: 2023-07-01 15:27:28


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Presentation and Participation FAQ] (in Japanese)
 

[Return to CAS Schedule Page]   /   [Return to VLD Schedule Page]   /   [Return to SIP Schedule Page]   /   [Return to MSS Schedule Page]   /  
 
 Go Top  Go Back   Prev VLD Conf / Next VLD Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan