Mon, Sep 29 PM 13:30 - 14:30 |
(1) |
13:30-14:30 |
[Invited Talk]
Phase-Adjustable Error Detection Flip-Flops with 2-Stage Hold Driven Optimization and Slack Based Grouping Scheme for Dynamic Voltage Scaling |
Masanori Kurimoto, Hiroaki Suzuki (Renesas Technology), Rei Akiyama, Tadao Yamanaka, Haruyuki Okuma (Renesas Design), Hidehiro Takata, Hirofumi Shinohara (Renesas Technology) |
|
14:30-14:45 |
Break ( 15 min. ) |
Mon, Sep 29 PM 14:45 - 15:35 |
(2) |
14:45-15:10 |
A DFG Mapping Algorithm for Flexible Engine/Generic ALU Array |
Masayuki Honma, Ryo Tamura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi, Ltd.) |
(3) |
15:10-15:35 |
FFT Design for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm |
Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi, Ltd.) |
|
15:35-15:50 |
Break ( 15 min. ) |
Mon, Sep 29 PM 15:50 - 17:05 |
(4) |
15:50-16:15 |
Schedulable Resouce Binding under Skew Optimization |
Takayuki Obata, Mineo Kaneko (JAIST) |
(5) |
16:15-16:40 |
Delay Variation-Aware Datapath Synthesis Based on Register Clustering |
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) |
(6) |
16:40-17:05 |
Design and Evalution of a Butterfly Circuit Using Selector Logic by Bit-Level Transformation |
Takeshi Namura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Print) |
Tue, Sep 30 AM 10:00 - 11:00 |
(7) |
10:00-11:00 |
[Invited Talk]
On the Order Statistics Applications to EDA, including Non Parametric Statistical Static Timing Analysis |
Masanori Imai (STARC/Tokyo Inst. Tech.) |
|
11:00-11:15 |
Break ( 15 min. ) |
Tue, Sep 30 AM 11:15 - 12:05 |
(8) |
11:15-11:40 |
Overlap-aware Analytical Placement Based on Stable-LSE |
Naoto Funatsu, Yasuhiro Takashima (Univ. of Kitakyushu) |
(9) |
11:40-12:05 |
A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages |
Yoshiaki Kurata, Yoichi Tomioka, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) |
|
12:05-13:30 |
Lunch Break ( 85 min. ) |
Tue, Sep 30 PM 13:30 - 14:20 |
(10) |
13:30-13:55 |
Fast configuration experiments of a large-gates optically reconfigurable gate array |
Mao Nakajima, Minoru Watanabe (Shizuoka Univ.) |
(11) |
13:55-14:20 |
Fast dynamic optically reconfigurable gate array VLSI |
Shinichi Kato, Minoru Watanabe (Shizuoka Univ.) |
|
14:20-14:35 |
Break ( 15 min. ) |
Tue, Sep 30 PM 14:35 - 15:25 |
(12) |
14:35-15:00 |
A programmable multi-context optical reconfigurable gate array using a PAL-SLM |
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.) |
(13) |
15:00-15:25 |
Variable linear transconductance OTA |
Masaki Ikemoto, Cong-Kha Pham (UEC) |