Wed, Feb 28 PM 【VLD】
14:00 - 15:15 |
| (1) |
14:00-14:25 |
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Masashi Tawada, Nozomu Togawa (Waseda Univ.) |
| (2) |
14:25-14:50 |
Set-Pair Routing Solver with Layer-by-layer Formulation on ILP |
Yasuhiro Takashima (Univ of Kitakyushu) |
| (3) |
14:50-15:15 |
High Level Datapath Synthesis for Enhanced Timing Tunability |
Mineo Kaneko (JAIST) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Wed, Feb 28 PM 【VLD】
15:30 - 17:10 |
| (4) |
15:30-15:55 |
A Template Routing Method Using SMT Solver for Double Via-Constrained Pair Symmetric Routing Problem |
Zuan Jo, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Mathieu Molongo, Makoto Minami, Katsuya Nishioka (JEDAT) |
| (5) |
15:55-16:20 |
Three-layer Bottleneck Channel Track Assignment for Pins Placed on Opposite Sides |
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Mathieu Molongo, Makoto Minami, Katsuya Nishioka (Jedat) |
| (6) |
16:20-16:45 |
Single Trunk Routing Problem for Generalized Channel |
Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi (Tokyo Tech) |
| (7) |
16:45-17:10 |
Research on Routing Method for Spacer-Is-Metal Type Self-Aligned Double Patterning |
Koki Tanaka, Takuto Amari, Kunihiro Fujiyoshi (TUAT) |
Thu, Feb 29 AM 【VLD】
09:20 - 11:00 |
| (8) |
09:20-09:45 |
A Scalable Mapping Method for Elastic CGRAs |
Makoto Saito, Takuya Kojima, Hideki Takase, Hiroshi Nakamura (UT) |
| (9) |
09:45-10:10 |
Instruction-set Extension Using Graph Neural Networks |
Ayumi Uki, Yuko Hara (TiTech) |
| (10) |
10:10-10:35 |
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() |
| (11) |
10:35-11:00 |
Distributed Task Migration Algorithm for 3D Stacked Chips and Evaluation with actual measurement |
Takahiro Kanamori, Songxiang Wang, Kimiyoshi Usami (SIT) |
| |
11:00-11:15 |
Break ( 15 min. ) |
Thu, Feb 29 AM 【ICD】
11:15 - 12:30 |
| (12) |
11:15-11:40 |
Design of RISC-V SoC with Post-quantum Encryption Algorithm Acceleration |
Jiyuan Xin, Makoto Ikeda (UTokyo) |
| (13) |
11:40-12:05 |
A Study of Edge AI & Distributed DB Computing Architecture for Edge-Centric Digital Twin |
Hiroshi Miyata (TAN), Kazutami Arimoto (Okayama Pref. Univ.), Atsushi Hayami, Hisayoshi Mizuno (TAN), Tomoyuki Yokogawa (Okayama Pref. Univ.) |
| (14) |
12:05-12:30 |
|
Shuhei Yokota, Rikuu Hasegawa, Kazuki Monta, Takaki Okidono, Takuji Miki, Makoto Nagata (Kobe Univercity) |
| |
12:30-14:00 |
Lunch Break ( 90 min. ) |
Thu, Feb 29 PM 【HWS】
14:00 - 15:15 |
| (15) |
14:00-14:25 |
Nano Artifact Metric Systems Resistant Against Clones Produced by Scanning Probe Lithography |
Akira Iwahashi, Naoki Yoshida, Katsunari Yoshioka (YNU), Tsutomu Matsumoto (AIST) |
| (16) |
14:25-14:50 |
Fundamental study on individual identification using electromagnetic characteristics unique to electronic devices |
Tsuyoshi Kobayashi, Mio Akahori, Takahiro Horiguchi (Mitsubishi Electric) |
| (17) |
14:50-15:15 |
|
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| |
15:15-15:30 |
Break ( 15 min. ) |
Thu, Feb 29 PM 【VLD】
15:30 - 17:10 |
| (18) |
15:30-15:55 |
[Memorial Lecture]
Design of Aging-Robust Clonable PUF Using an Insulator-Based ReRAM for Organic Circuits |
Kunihiro Oshima (Kyoto Univ.), Kazunori Kuribara (AIST), Takashi Sato (Kyoto Univ.) |
| (19) |
15:55-16:20 |
[Memorial Lecture]
Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits |
Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi (Osaka Univ.) |
| (20) |
16:20-16:45 |
[Memorial Lecture]
Logic Locking over TFHE for Securing User Data and Algorithms |
Kohei Suemitsu, Kotaro Matsuoka, Takashi Sato, Masanori Hashimoto (Kyoto Univ.) |
| (21) |
16:45-17:10 |
[Memorial Lecture]
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow |
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu (Tokyo Tech) |
Fri, Mar 1 AM 【VLD】
09:20 - 10:35 |
| (22) |
09:20-09:45 |
|
Kei Nakao, Yukihide Kohira, Hiroshi Saito, Yoichi Tomioka (Univ. of Aizu) |
| (23) |
09:45-10:10 |
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| (24) |
10:10-10:35 |
Fault Detectable Convolutional Neural Network Circuits With Dual Modular Redundancy Based on Mixed-precision Quantization |
Yamato Saikawa, Yuta Owada, Yoichi Tomioka, Hiroshi Saito, Yukihide Kohira (UoA) |
| |
10:35-10:50 |
Break ( 15 min. ) |
Fri, Mar 1 AM 【HWS】
10:50 - 12:30 |
| (25) |
10:50-11:15 |
Pseudo-random Number Generator Design Robust against Fault Injection Attacks |
Sota Kado, Mingyu Yang, Yuko Hara (Tokyo Tech) |
| (26) |
11:15-11:40 |
Investigation of electromagnetic irradiation noise reduction by on-chip LDOs |
Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata (Kobe Univ.) |
| (27) |
11:40-12:05 |
Improved Ring Oscillator Sensor for Laser Fault Injection Detection on FPGA |
Masaki Chikano (YNU), Shungo Hayashi, Junichi Sakamoto (YNU/AIST), Tsutomu Matsumoto (YNU) |
| (28) |
12:05-12:30 |
Security Evaluation of Fault Analysis for SuperSonic |
Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) |
| |
12:30-14:00 |
Lunch Break ( 90 min. ) |
Fri, Mar 1 PM 【VLD】
14:00 - 15:15 |
| (29) |
14:00-14:25 |
High-Level Synthesis Method for Python Considering Runtime Profiling |
Yusuke Suzuki, Makoto Ikeda (UTokyo) |
| (30) |
14:25-14:50 |
Modeling of Thin-Film Ferroelectric Memcapacitors Based on Gaussian Process Regression and its evaluation |
Ryoga Urata (KIT), Taiyo Shinoda, Mutsumi Kimura (Ryukoku Univ.), Michihiro Shintani (KIT) |
| (31) |
14:50-15:15 |
Defect Coverage Estimation by Sampling in Testing Power TSV |
Koutaro Hachiya, Yudai Kawakami (THU) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Fri, Mar 1 PM 【HWS】
15:30 - 17:10 |
| (32) |
15:30-15:55 |
A Pipelined NTT Transformer and its Extension Scheme Designed for the Digital Signature Scheme Crystals-Dilithium |
Pengfei Sun, Makoto Ikeda (Tokyo Univ.) |
| (33) |
15:55-16:20 |
Hardware Design Based on Full Parameter Support and Parallelism Optimization for Key Encapsulation Mechanism FIPS203 |
Yuto Nakamura, Makoto Ikeda (UTokyo) |
| (34) |
16:20-16:45 |
An Efficient Hardware Approach for High-Speed SPHINCS+ Signature Generation |
Yuta Takeshima, Makoto Ikeda (The Univ. of Tokyo) |
| (35) |
16:45-17:10 |
A Study on Post-Quantum Signature QR-UOV Hardware |
Hiroshi Amagasa, Rei Ueno (Tohoku Univ.), Kimihiro Yamakoshi, Kouha Kinjo, Rika Akiyama (NTT), Naofumi Homma (Tohoku Univ.) |
Sat, Mar 2 AM 【HWS】
09:20 - 10:35 |
| (36) |
09:20-09:45 |
Countermeasure on AI Hardware against Adversarial Examples |
Kosuke Hamaguchi, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) |
| (37) |
09:45-10:10 |
Demonstrating a Real Car Covered with Infra-red-cut Films to Hide itself from LiDAR |
Yuki Fukatsu, Akira Iwahashi, Naoki Yoshida, Tsutomu Matsumoto (YNU) |
| (38) |
10:10-10:35 |
Feasibility Study of Instrumentation Security for Infrastructure Monitoring Camera |
Nagisa Nishimura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Noriyuki Miura (Osaka Univ.) |
| |
10:35-10:50 |
Break ( 15 min. ) |
Sat, Mar 2 AM 【HWS】
10:50 - 12:30 |
| (39) |
10:50-11:15 |
Design of General Hardware for Optimal Strategy in Isogeny-Based Post-Quantum Cryptography |
Kosei Nakamura, Makoto Ikeda (UT) |
| (40) |
11:15-11:40 |
Composable Security in High Level Synthesis for Cipher Circuit Implementation |
Mingyu Yang, Gento Hiruma (Titech), Kazuo Sakiyama, Yang Li (UEC), Yuko Hara-Azumi (Titech) |
| (41) |
11:40-12:05 |
eFPGA-based IP Protection of Embedded Processor Design |
Tomosuke Ichioka, Tanvir Ahmed, Yuko Hara (Tokyo Tech) |
| (42) |
12:05-12:30 |
A Study on formal verification of GF(2^m) arithmetic circuits including states |
Kazuho Sakoda (SCU/Kobe Univ.), Yasuyoshi Uemura (SCU), Naofumi Homma (Tohoku Univ.) |
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