Wed, Dec 5 AM 09:30 - 10:45 |
(1) VLD |
09:30-09:55 |
Design Automation and Optimal Architecture of NLoC |
Yuto Umeda, Shigeru Yamashita (Ritsumeikan Univ.) |
(2) VLD |
09:55-10:20 |
A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones |
Yusuke Funabashi, Atsuya Shibata, Shunsuke Negoro (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) |
(3) VLD |
10:20-10:45 |
Prototyping of Real-time Computer-Aided Diagnosis System for Colorectal Endoscopic Movies and Images with Machine Learning |
Takumi Okamoto, Masayuki Odagawa, Koujiroh Takebayashi, Mikihisa Nagano, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (JR Hiroshima Hospital), Shinji Tanaka (Hiroshima Univ.), Takayuki Sugawara, Hiroshi Toishi, Masayuki Tsuji, Nobuo Tamba (Cadence, Japan) |
Wed, Dec 5 AM 09:55 - 10:45 |
(4) RECONF |
09:55-10:20 |
Development of Software/Hardware Cooperative System for Radiosity Method using High-Level Synthesis with an FPGA |
Kotaro Tamura, Tetsu Narumi (UEC univ.) |
(5) RECONF |
10:20-10:45 |
An FPGA implementation of Tri-state YOLOv2 using Intel OpenCL |
Youki Sada, Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) |
Wed, Dec 5 AM 09:55 - 10:45 |
(6) |
09:55-10:20 |
|
(7) |
10:20-10:45 |
|
|
10:45-11:00 |
Break ( 15 min. ) |
Wed, Dec 5 AM 11:00 - 12:00 |
(8) |
11:00-12:00 |
[Keynote Address]
Challenge of Post CMOS Circuit Technologies for AI Hardware |
Takahiro Hanyu (Tohoku Univ.) |
|
12:00-13:00 |
Lunch Break ( 60 min. ) |
Wed, Dec 5 PM 13:00 - 14:00 |
(9) |
13:00-14:00 |
[Keynote Address]
|
Hiroki Nakahara (Titech) |
|
14:00-14:15 |
Break ( 15 min. ) |
Wed, Dec 5 PM 14:15 - 15:30 |
(10) VLD |
14:15-14:40 |
Basic Evaluation of Netlist Function Inference using GCN |
Hiroki Oyama, Motoki Amagasaki, Masahiro Iida (kumamoto Univ.), Hiroaki Yasuda, Hiroto Ito (MITSUBISHI ELECTRIC ENGINEERING) |
(11) VLD |
14:40-15:05 |
Improved Routing Method for Two Layer Self-Aligned Double Patterning |
Shoya Tamura, Kunihiro Fujiyoshi (TUAT) |
(12) VLD |
15:05-15:30 |
Horizontal Wireless Bus for Free-Form SiP |
Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai (The Univ. of Tokyo) |
|
15:30-15:45 |
Break ( 15 min. ) |
Wed, Dec 5 PM 15:45 - 17:30 |
|
- |
|
Thu, Dec 6 AM 09:00 - 10:15 |
(13) RECONF |
09:00-09:25 |
Resources Utilization of Fine-grained Overlay Architecture |
Theingi Myint (Kumamoto), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto) |
(14) RECONF |
09:25-09:50 |
Transparent Acceleration Method for Network Function Virtualization Using FPGA |
Yoshikazu Watanabe, Yuki Kobayashi, Takashi Takenaka, Baba Hiroshi (NEC) |
(15) RECONF |
09:50-10:15 |
An Evaluation of Acceleration Framework to Exploit TCAM implemented on FPGA |
Takefumi Miyoshi (WasaLab/e-trees.Japan), Satoshi Funada (e-trees.Japan) |
Thu, Dec 6 AM 09:00 - 10:15 |
(16) |
09:00-09:25 |
|
(17) |
09:25-09:50 |
|
(18) |
09:50-10:15 |
|
Thu, Dec 6 AM 09:00 - 10:15 |
(19) VLD |
09:00-09:25 |
Stochastic Number Generation Considering Trade-off between Error and Overhead |
Yudai Sakamoto, Shigeru Yamashita (Ritsumeikan Univ.) |
(20) VLD |
09:25-09:50 |
Quality determination of logic element placement using deep learning in fine grain reconfigurable device MPLD |
Hidehito Fujiishi, Tokio Kamada, Tetsuo Hironaka, Kazuya Tanigawa, Atsushi Kubota (Hiroshima city Univ.) |
(21) VLD |
09:50-10:15 |
Secure PUF Authentication Method against Machine Learning Attack |
Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) |
|
10:15-10:30 |
Break ( 15 min. ) |
Thu, Dec 6 AM 10:30 - 11:45 |
(22) RECONF |
10:30-10:55 |
Multi-FPGA implementation of deep learning applications |
Kazusa Musha, Akram Ben Ahmed (Keio Univ.), Kudoh Tomohiro (Univ. of Tokyo), Hideharu Amano (Keio Univ.) |
(23) RECONF |
10:55-11:20 |
A Tiny Memory implementation on an FPGA using Feature-Map Separable Convolution Technique |
Akira Jinguji, Simpei Sato, Hiroki Nakahara (titech) |
(24) RECONF |
11:20-11:45 |
Hardware implementation of ECG signals outlier detector trained by Sparse Robust Deep Autoencoder |
Naoto Soga, Shimpei Sato, Hiroki Nakahara (Titech) |
Thu, Dec 6 AM 10:30 - 11:45 |
(25) DC |
10:30-10:55 |
|
|
(26) DC |
10:55-11:20 |
On the Generation of Random Capture Safe Test Vectors Using Neural Networks |
Sayuri Ochi, Kenichirou Misawa, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.) |
(27) DC |
11:20-11:45 |
|
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
Thu, Dec 6 AM 10:30 - 11:45 |
(28) VLD |
10:30-10:55 |
A Case Study on Memory Architecture Exploration for FPGA-based Manycores |
Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) |
(29) VLD |
10:55-11:20 |
Improved Thread Execution for GPU-oriented OpenCL Programs on Multicore Processors |
Takafumi Miyazaki, Hayato Hidari, Naohisa Hojo (Ritsumeikan Univ), Naohisa Hojo (Osaka Univ), Hiroyuki Tomiyama (Ritsumeikan Univ) |
(30) VLD |
11:20-11:45 |
An FPGA-NIC Based 40-Gbit/s Automated Response Circuit for Invalid DNS Packets to Suppress CPU Utilization of DNS Content Server |
Shoko Ohteru, Saki Hatta, Tomoaki Kawamura (NTT), Koji Yamazaki (NTT-AT), Takahiro Hatano, Akihiko Miyazaki, Koyo Nitta (NTT) |
|
11:45-13:00 |
Lunch Break ( 75 min. ) |
Thu, Dec 6 PM 13:00 - 13:45 |
(31) CPSY |
13:00-13:45 |
[Invited Talk]
What I should do beside dedicated AI hardwares |
Yasuhiko Nakashima (NAIST) |
Thu, Dec 6 PM 13:00 - 14:40 |
(32) DC |
13:00-13:25 |
Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC |
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) |
(33) DC |
13:25-13:50 |
Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips |
Takaaki Kato (KIT), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (KIT) |
(34) DC |
13:50-14:15 |
Study on the Applicability of ATPG Pattern for DFT Circuit |
Kohki Taniguchi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) |
(35) DC |
14:15-14:40 |
Register-Transfer Level Exploration of Segments Utilizable for Scan Path Synthesis |
Sho Yuasa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
Thu, Dec 6 PM 13:00 - 14:15 |
(36) VLD |
13:00-13:25 |
An efficient SAT-attack algorithm against logic encryption |
Yusuke Matsunaga (Kyushu Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) |
(37) VLD |
13:25-13:50 |
A Hybrid Method Using Monte-Carlo Tree Search and Gibbs Sampling Method for Solving Motif Extraction Problems |
Yusuke Yuasa, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (HCU) |
(38) VLD |
13:50-14:15 |
|
Hiroki Nishimoto, Takashi Nakada, Yasuhiko Nakashima (NAIST) |
Thu, Dec 6 PM 14:00 - 14:50 |
(39) RECONF |
14:00-14:25 |
Triple modular redundancy optically reconfigurable gate array |
Toru Yoshinaga, Minoru Watanabe (Shizuoka Univ.) |
(40) RECONF |
14:25-14:50 |
FPGA implementation of a robot control algorithm |
Yusuke Takaki, Minoru Watanabe (Shizuoka Univ.), Kentaro Sano (Riken) |
Thu, Dec 6 PM 14:30 - 15:15 |
(41) |
14:30-15:15 |
|
Thu, Dec 6 PM 14:55 - 16:10 |
(42) ICD |
14:55-15:20 |
Design guideline of ground structure in slow wave transmission line |
Tomohiro Kobayashi, Syuhei Amakawa, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ) |
(43) ICD |
15:20-15:45 |
Millimeter wave band CMOS low noise amplifier design |
Kyoya Takegawa, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.) |
(44) ICD |
15:45-16:10 |
Design method of millimeter wave CMOS amplifier circuit with flat frequency characteristics |
Shota Kohara, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.) |
Thu, Dec 6 PM 15:30 - 16:15 |
(45) |
15:30-16:15 |
|
Thu, Dec 6 PM 15:30 - 16:45 |
(46) |
15:30-15:55 |
|
(47) VLD |
15:55-16:20 |
Malleable Task Scheduling for Energy Minimization on Heterogeneous Multicores |
Hiroki Nishikawa, Kana Shimada (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) |
(48) VLD |
16:20-16:45 |
Communication-Aware Scheduling for Data-Parallel Tasks |
Kana Shimada (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) |
Thu, Dec 6 PM 18:30 - 20:30 |
|
- |
|
Fri, Dec 7 AM 09:00 - 10:15 |
(49) CPSY |
09:00-09:25 |
A Scalable Multi-Path Selection Method for High-Throughput Interconnection Networks |
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) |
(50) |
09:25-09:50 |
|
(51) |
09:50-10:15 |
|
Fri, Dec 7 AM 09:25 - 10:15 |
(52) ICD |
09:25-09:50 |
Design method of millimeter wave CMOS oscillator with high efficiency |
Tomoya Takiwaki, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.) |
(53) ICD |
09:50-10:15 |
A Ring-VCO Using Bootstrap Inverter |
Akinori Yamamoto, Cong-Kha Pham (UEC) |
Fri, Dec 7 AM 09:00 - 10:15 |
(54) VLD |
09:00-09:25 |
Design and fabrication of characteristics measurement circuit for CMOS-compatible ultra-low-power non-volatile memory element using FiCC |
Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) |
(55) VLD |
09:25-09:50 |
Flip-Flops with different retention characteristics for process variation estimation |
Kento Fukazawa, Shinichi Nishizawa, Kazuhito Ito (Saitama Univ.) |
(56) VLD |
09:50-10:15 |
A study on estimating the degradation of critical path delay using replica sensors |
Kunihiro Oshima, Son Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) |
|
10:15-10:30 |
Break ( 15 min. ) |
Fri, Dec 7 AM 10:30 - 11:30 |
(57) |
10:30-11:30 |
[Keynote Address]
Tensor Processing Unit: A processor for neural network designed by Google |
Kazunori Sato (Google) |
|
11:30-12:30 |
Lunch Break ( 60 min. ) |
Fri, Dec 7 PM 12:30 - 13:30 |
(58) |
12:30-13:30 |
[Keynote Address]
AI in medical imaging diagnosis |
Hiroshi Fujita (Gifu Univ.) |
|
13:30-13:45 |
Break ( 15 min. ) |
Fri, Dec 7 PM 13:45 - 15:00 |
(59) CPSY |
13:45-14:10 |
|
|
(60) |
14:10-14:35 |
|
(61) CPSY |
14:35-15:00 |
An Efficient Multiplier Employing Time-Encoded Stochastic Computing Circuit |
Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima (NAIST) |
Fri, Dec 7 PM 13:45 - 15:00 |
(62) ICD |
13:45-14:10 |
Autonomous SCM capacity adjustment method in SCM/NAND flash hybrid storage |
Chihiro Matsui, Ken Takeuchi (Chuo Univ.) |
(63) ICD |
14:10-14:35 |
Ultra-long-term Measurement of Aging Degradation on Ring Oscillators by using FPGA and Micro Controller |
Hiroki Nakano (KIT), Ryo Kishida (TUS), Jun Furuta, Kazutoshi Kobayashi (KIT) |
(64) ICD |
14:35-15:00 |
Analysis of Conductive Power Noise Characteristics in Digital IC Chips between two Different IC Packaging Structures |
Akihiro Tsukioka, Kosuke Jike, Koh Watanabe, Noriyuki Miura, Makoto Nagata (Kobe Univ.) |
Fri, Dec 7 PM 13:45 - 15:00 |
(65) VLD |
13:45-14:10 |
A Radiation-hard Low-delay Flip-Flop with Stacking Structure for SOI Process |
Mitsunori Ebara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) |
(66) VLD |
14:10-14:35 |
Process Variation-aware Model-based OPC using 0-1 Quadratic Programming |
Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama, Shigeki Nojima (TMC) |
(67) VLD |
14:35-15:00 |
Comparison of Machine Learning-Based Lithography Hotspot Detection Methods under Optimized Hyperparameters |
Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
|
15:00-15:15 |
Break ( 15 min. ) |
Fri, Dec 7 PM 15:15 - 16:05 |
(68) CPSY |
15:15-15:40 |
Real Chip Implementation of a verification scheme for an Inductive-Coupling ThruChip Interface |
Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Hideharu Amano (Keio Univ.) |
(69) CPSY |
15:40-16:05 |
. |
Tomohiro Totoki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) |
Fri, Dec 7 PM 15:15 - 16:55 |
(70) CPM |
15:15-15:40 |
Quarter Video Graphics Array Image Sensor with Linear and Wide-Dynamic-Range Output Developed by Pixel-Wise 3D Integration |
Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi (NHK), Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto (Univ. of Tokyo) |
(71) IE |
15:40-16:05 |
A 4-cell per Pixel Structure Image Sensor with Gradient-Based Motion Estimation Function |
Tomohiro Aratani, Takayuki Hamamoto (TUS) |
(72) IE |
16:05-16:30 |
A Method of Image Processing for Extraction of Plant Growth Indicators toward Development of Plant Growth Estimation Technologies |
Yasunori Sakane, Takumi Okamoto, Tetsushi Koide (Hiroshima Univ.), Atsushi Ogawa, Masashi Komine, Chiharu Sone, Kyoko Toyofuku, Takahiro Kamata, Ken Kimura, Yoko Ishikawa, Yoshihiro Kaneta, Yukio Yaji, Yoshikazu Ishii (Akita Prefectural Univ.), Toshihiro Kasama, Wojciech Bula, Yoshishige Endo, Ryo Miyake (The Univ. of Tokyo) |
(73) IE |
16:30-16:55 |
Non-Linear Signal Processing Super Resolution for 8K Endoscope Camera
-- Real-Time Super Resolution for 8K Endoscope -- |
Chinatsu Mori, Seiichi Gohshi (Kogakuin Univ.), Kenkichi Tanioka (Medical Consotium), Hiromasa Yamashita (Kairos) |