Wed, May 19 PM System Design and Optimization I Chair: Akihisa Yamda (Sharp) 14:15 - 15:55 |
(1) |
14:15-14:40 |
Automatic Clock Gating Generation Through Power-Optimal Control Signal Selection
Xin Man (Waseda University), Takashi Horiyama (Saitama University), Shinji Kimura (Waseda Univ.) |
(2) |
14:40-15:05 |
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(3) |
15:05-15:30 |
Post-Scheduling Frequency Assignment for High-Level Synthesis
Ru Liu, Song Chen, Takeshi Yoshimura (Waseda Univ.) |
(4) VLD |
15:30-15:55 |
High-Level Synthesis with Floorplan for GDR Architectures and its Evaluation |
Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
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15:55-16:10 |
Break ( 15 min. ) |
Wed, May 19 PM Dependable Design Chair: Nozomu Togawa (Waseda Univ.) 16:10 - 17:25 |
(5) VLD |
16:10-16:35 |
Highly Accurate Approximate Methods for Soft Error Tolerance Estimation for Sequential Circuits |
Naoki Shirobayashi, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) |
(6) VLD |
16:35-17:00 |
An Approximate Method for Steady State Probability Calculation based on FSM Splitting |
So Hasegawa, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) |
(7) VLD |
17:00-17:25 |
Error Propagation Probability-based Selective TMR for Reliable Coarse-Grained Reconfigurable Architecture |
Hiroshi Yuasa, Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) |
Thu, May 20 AM System Design and Optimizaion II Chair: Naoyuki Hoshi (Mitsubishi Electric) 10:00 - 11:40 |
(8) VLD |
10:00-10:25 |
3D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link |
Makoto Saen, Kenichi Osada, Yasuyuki Okuma (Hitachi), Yasuhisa Shimazaki (Keio Univ./Renesas Technology), Itaru Nonomura (Renesas Technology), Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Tadahiro Kuroda (Keio Univ.) |
(9) VLD |
10:25-10:50 |
Implementation of error correction method on small area and low power consumption processor for the capsular detrusor pressure measurement system |
Hiroki Ohsawa, Tomohiro Kondo, Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
(10) |
10:50-11:15 |
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(11) |
11:15-11:40 |
A general neural network architecture for efficient FPGA-based implementation
Lin Zhen, Dong Yipng, Watanabe Takahiro (Waseda Univ.) |
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11:40-13:05 |
Lunch ( 85 min. ) |
Thu, May 20 PM Circuit Optimization Technique Chair: Kenshu Seto (Tokyo City Univ.) 13:05 - 14:45 |
(12) VLD |
13:05-13:30 |
A Wide-Range Clock Synchronizer with Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS Control |
Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu (Hitachi), Yoshihiko Yasu, Koichiro Ishibashi (Renesas) |
(13) VLD |
13:30-13:55 |
Temperature-dependent model for break-even time in fine-grain power gating and adaptive control based on the temperature dependence |
Kimiyoshi Usami, Tatsunori Hashida (Shibaura Inst. Tech.) |
(14) VLD |
13:55-14:20 |
An Efficient Congested Area Specification And Congestion Relaxation by 45 Degree Line for Single Layer Printed Circuit Board Rouitng |
Kyosuke Shinoda (Tokyo Tech), Yukihide Kohira (UoA), Atsushi Takahashi (Osaka Univ.) |
(15) VLD |
14:20-14:45 |
Variation Modeling of Current Sources by D/A Converter Analysis |
Bo Liu, Qing Dong, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu) |