Mon, Mar 4 PM
13:50 - 15:05 |
| (1) |
13:50-14:15 |
A Logic Simplification Algorithm with Multiple Stuck-at Faults for Error Tolerant Application |
Junpei Kamei, Shingo Matsuki, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
| (2) |
14:15-14:40 |
Acceleration of current-threshold determination toward on-line IDDQ testing through parameter estimation |
Michihiro Shintani, Takashi Sato (Kyoto Univ.) |
| (3) |
14:40-15:05 |
Self-Compensation of Manufacturing Variability using On-Chip Sensors |
Yuma Higuchi, Masanori Hashimoto, Takao Onoye (Osaka Univ.) |
| |
15:05-15:20 |
Break ( 15 min. ) |
Mon, Mar 4 PM
15:20 - 17:00 |
| (4) |
15:20-15:45 |
APR-based Legalization Method |
Shota Hirae, Maho Ishikawa, Yasuhiro Takashima (Univ. of Kitakyusyu) |
| (5) |
15:45-16:10 |
TSV-aware Analytical Placement |
Koji Morita, Yasuhiro Takashima (Univ. of Kitakyushu) |
| (6) |
16:10-16:35 |
Analytical Placement for Rectilinear Blocks |
Tomoaki Gotanda, Yasuhiro Takashima (Univ. of Kitakyusyu) |
| (7) |
16:35-17:00 |
The minimum perturbation placement realization for convex blocks |
Hiroki Matsugano, Shota Hirae, Yasuhiro Takashima (Univ. of Kitakyushu) |
Tue, Mar 5 AM
10:00 - 11:40 |
| (8) |
10:00-10:25 |
An Automatic Nested Loop Pipelining method from C level behavior description |
Masahiro Nambu, Takashi Kambe (Kinki Univ.) |
| (9) |
10:25-10:50 |
An Acceleration method and its evaluation for Coarse Grained Reconfigurable Circuit Synthesis |
Nobuyuki Araki, Takashi Kambe (Kinki Univ.) |
| (10) |
10:50-11:15 |
High Level Resynthesis Approach of Reusable RTL Property |
Msaato Tatsuoka, Mineo Kaneko (JAIST) |
| (11) |
11:15-11:40 |
A Multi-Task Scheduling and Allocation for Highly Reliable Network-on-Chip |
Hiroshi Saito (Univ. of Aizu), Tomohiro Yoneda (NII), Yuichi Nakamura (NEC) |
| |
11:40-13:00 |
Break ( 80 min. ) |
Tue, Mar 5 PM
13:00 - 13:50 |
| (12) |
13:00-13:50 |
[Invited Talk]
Cyber-Physical Systems and LSI Design Technologies |
Shinpei Kato, Masato Edahiro (Nagoya Univ.) |
| |
13:50-14:05 |
Break ( 15 min. ) |
Tue, Mar 5 PM
14:05 - 15:20 |
| (13) |
14:05-14:30 |
An Optimal Design Method for Input Signals of Small SoG-LCDs and Its Evaluation |
Taichi Suizu, Shuji Tsukiyama (Chuo Univ.) |
| (14) |
14:30-14:55 |
A Routing Method Considering Wirelength of Each Net for Single Layer PCB Routing |
Kyosuke Shinoda, Atsushi Takahashi (Tokyo Inst. of Tech.) |
| (15) |
14:55-15:20 |
A Parallel Global Routing Method Sharing Routing Regions for Multi-Core Processors |
Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
| |
15:20-15:35 |
Break ( 15 min. ) |
Tue, Mar 5 PM
15:35 - 16:50 |
| (16) |
15:35-16:00 |
[Memorial Lecture]
Line Sharing Cache: Exploring Cache Capacity with Frequent Line Value Locality |
Keitarou Oka, Hiroshi Sasaki, Koji Inoue (Kyushu Univ.) |
| (17) |
16:00-16:25 |
[Memorial Lecture]
An Adaptive Current-Threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation |
Michihiro Shintani, Takashi Sato (Kyoto Univ.) |
| (18) |
16:25-16:50 |
[Memorial Lecture]
Network Simplex Method Based Multiple Voltage Scheduling in Power-Efficient High-Level Synthesis |
Cong Hao, Song Chen, Takeshi Yoshimura (Waseda Univ.) |
Wed, Mar 6 AM
10:30 - 11:45 |
| (19) |
10:30-10:55 |
A worst-case-aware design methodology for oscillator-based true random number generator with stochastic behavior modeling |
Takehiko Amaki, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Takao Onoye (Osaka Univ.) |
| (20) |
10:55-11:20 |
Design and Evalution of Sleep Control Circuit for Fine-grain Power Gating |
Yoshihiro Tsurui, Kimiyoshi Usami, Tatsunori Hashida, Tetsuya Muto, Yuki Shimada (Shibaura Inst. of Tech.) |
| (21) |
11:20-11:45 |
a design of COMET II processor as an embedded softcore processor |
Kei Kimoto, Tomonori Izumi (Ritsumeikan Univ.) |
| |
11:45-13:15 |
Break ( 90 min. ) |
Wed, Mar 6 PM
13:15 - 14:30 |
| (22) |
13:15-13:40 |
Delay Analysis of Reconvergent Paths with Correlation |
Masatsugu Hosoki, Hiroshi Sasaki, Yasuhiro Takashima (Univ. of Kitakyushu) |
| (23) |
13:40-14:05 |
A Delay Control Circuit with Channel Length Decomposition and Its Application |
Yuichi Toyota, Yuki Nakashima, Toru Fujimura, Shigetoshi Nakatake (Univ of Kitakyushu) |
| (24) |
14:05-14:30 |
Test Planning for Post-Silicon Skew Tuning Based on Graph Partitioning |
Mineo Kaneko (JAIST) |
| |
14:30-14:45 |
Break ( 15 min. ) |
Wed, Mar 6 PM
14:45 - 16:00 |
| (25) |
14:45-15:10 |
Probability Driven Hierarchical Fault Analysis System and its Implementation |
Hikaru Goto, Masaya Yoshikawa (Meijo Univ.) |
| (26) |
15:10-15:35 |
Trojan Circuit for Fault Analysis Countermeasure and its Implementation |
Takaya Tsukadaira, Daisuke Matsushima (Meijo Univ.), Takeshi Kumaki (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.) |
| (27) |
15:35-16:00 |
Robust Redundant Circuit Structure to Mitigate Wearout by Reversing Register Values |
Shogo Okada, Masaki Masuda (Kyoto Inst. of Tech.), Jun Yao, Hajime Shimada (NAIST), Kazutoshi Kobayashi (Kyoto Inst. of Tech.) |
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