ken-system: Advance Program - 2023-11-VLD-DC-RECONF-ICD-IPSJ-SLDM

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Technical Committee on VLSI Design Technologies (VLD)

[schedule] [select]

Chair		Shigetoshi Nakatake (Univ. of Kitakyushu)
Vice Chair		Yuichi Sakurai (Hitachi)
Secretary		Yukihiro Sasagawa (Socionext), Masashi Imai (Hirosaki Univ.)
Assistant		Takuma Nishimoto (Hitachi)

Technical Committee on Integrated Circuits and Devices (ICD)

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Chair		Makoto Ikeda (Univ. of Tokyo)
Vice Chair		Hayato Wakabayashi (Sony Semiconductor Solutions)
Secretary		Yoshiaki Yoshihara (Kioxia), Kosuke Miyaji (Shinshu Univ.)
Assistant		Ryo Shirai (Kyoto Univ.), Jun Shiomi (Osaka Univ.), Takeshi Kuboki (Kumamoto University)

Technical Committee on Dependable Computing (DC)

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Chair		Tatsuhiro Tsuchiya (Osaka Univ.)
Vice Chair		Toshinori Hosokawa (Nihon Univ.)
Secretary		Masayuki Arai (Nihon Univ.), Kazuteru Namba (Chiba Univ.)

Technical Committee on Reconfigurable Systems (RECONF)

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Chair		Yoshiki Yamaguchi (Tsukuba Univ.)
Vice Chair		Yasushi Inoguchi (JAIST), Tomonori Izumi (Ritsumeikan Univ.)
Secretary		Yuuki Kobayashi (NEC), Yukinori Sato (Toyohashi Univ. of Tech.)
Assistant		Yukitaka Takemura (INTEL), Yasunori Osana (Kumamoto Univ.)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)

[schedule] [select]

Chair		Hiroyuki Ochi (Ritsumeikan Univ.)
Secretary		Takashi Imagawa (Meiji Univ.), Ryo Kishida (Toyama Prefectural Univ.), Yuki Tanaka (HITACHI), Tomonori Igarashi (Renesas)

Conference Date	Wed, Nov 15, 2023 13:00 - 18:00 Thu, Nov 16, 2023 09:30 - 20:00 Fri, Nov 17, 2023 09:10 - 16:30
Topics	Design Gaia 2023 -New Field of VLSI Design-
Conference Place
Registration Fee	This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on VLD, DC, RECONF, ICD.

	13:00-13:10	Opening ( 10 min. )
Wed, Nov 15 PM 13:10 - 14:25
(1) VLD	13:10-13:35	N/A	Kota Hisafuru, Nozomu Togawa (Waseda Univ.)
(2) VLD	13:35-14:00	Loop optimization method for machine learning model in hardware-Trojan Detection	Ryotaro Negishi, Nozomu Togawa (Waseda Univ.)
(3) VLD	14:00-14:25
Wed, Nov 15 PM 13:10 - 14:25
(4) ICD	13:10-13:35	Frequency Dependence of Soft Error Rates Induced by Alpha-Particle and Heavy Ion	Haruto Sugisaki, Ryuichi Nakajima, Shotaro Sugitani, Jun Furuta, Kazutoshi Kobayashi (KIT)
(5) ICD	13:35-14:00	Data Pattern Dependence of the Total Ionizing Dose Effect in Floating-gate and Charge-trap TLC NAND flash memories	Taiki Ozawa, Jun Furuta, Kazutoshi Kobayashi (KIT)
(6) ICD	14:00-14:25	Evaluation of SEU Sensitivity by Alpha-Particle on PMOS and NMOS Transistors in a 65 nm bulk Process	Keita Yoshida, Ryuichi Nakajima, Shotaro Sugitani, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi (KIT)
	14:25-14:40	Break ( 15 min. )
Wed, Nov 15 PM 14:40 - 15:55
(7) VLD	14:40-15:05
(8) VLD	15:05-15:30	N/A	Soma Kawakami (Waseda Univ.), Kentaro Ohno, Dema Ba, Satoshi Yagi, Junji Teramoto (NTT), Nozomu Togawa (Waseda Univ.)
(9) VLD	15:30-15:55	Error Correction Decoder of the Surface Code designed in a 22-nm Bulk Process for Fault Torelant Quantum Computers	Ren Aoyama (KIT), Junichiro Kadomoto (UTokyo), Kazutoshi Kobayashi (KIT)
Wed, Nov 15 PM 14:40 - 16:20
(10) ICD	14:40-15:05	A 183.4 nJ/inference 152.8 µW Single-Chip Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application	Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda (UTokyo)
(11) ICD	15:05-15:30	Co-design of Strong Lottery Ticket Hypothesis and FeFET-based CiM	Kenshin Yamauchi, Ayumu Yamada, Naoko Misawa, Seong-Kun Cho, Kasidit Toprasertpong, Shinichi Takagi, Chihiro Matsui, Ken Takeuchi (Univ. of Tokyo)
(12) ICD	15:30-15:55	*	Itsuki Akeno, Hiro Yamazaki, Tetsuya Asai, Kota Ando (Hokkaido Univ)
(13) ICD	15:55-16:20	Preliminary Data-Pattern Analysis towards Energy-Efficient Adaptive In-Cache Computing for CNN Accelerations	Zhengpan Fei, Koji Inoue (Kyushu Univ.)
Wed, Nov 15 PM 16:20 - 18:00
(14)	16:20-18:00
Thu, Nov 16 AM 09:30 - 10:45
(15) VLD	09:30-09:55	Leakage-current Based Charge Accumulating Aging Sensor Circuit and Evaluation of NBTI Using Fabricated Chips	Mina Fukushima, Songxiang Wang, Kaito Nagai, Kimiyoshi Usami (SIT)
(16) VLD	09:55-10:20	MTJ-PUF with Input Decoder and Evaluation of Machine Learning Resistance	Takumi Kikuchi, Kimiyoshi Usami (SIT)
(17) VLD	10:20-10:45	Proposal of MTJ-based non-volatile flip-flops using reference resistance and Two-step Store Control	Kousei Kaizu, Kimiyoshi Usami (SIT)
Thu, Nov 16 AM 09:30 - 10:45
(18) ICD	09:30-09:55	Computation-in-Memory Generating Approximate Random Weight for Neuromorphic Computing	Naoko Misawa, Shunsuke Koshino, Chihiro Matsui, Ken Takeuchi (Univ. of Tokyo)
(19) ICD	09:55-10:20	Quantization Method of Computation-in-Memory for 1/10 Memory Size Vision Transformer	Naoko Misawa, Ryuhei Yamaguchi, Ayumu Yamada, Chihiro Matsui, Ken Takeuchi (Univ. of Tokyo)
(20) ICD	10:20-10:45	Design and Error-tolerance of FeFET-based CiM for Hyperdimensional Computing	Chihiro Matsui, Eitaro Kobayashi, Naoko Misawa, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi (Univ. of Tokyo)
	10:45-11:00	Break ( 15 min. )
Thu, Nov 16 AM 11:00 - 12:00
(21)	11:00-11:50
(22)	11:50-12:00
	12:00-13:20	Lunch Break ( 80 min. )
Thu, Nov 16 PM 13:20 - 14:35
(23) VLD	13:20-13:45	Tamper Resistance Evaluation on FPGA for Low-Latency Cipher Sonic	Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
(24) VLD	13:45-14:10
(25) VLD	14:10-14:35	Implementation of Neural Networks in Memory-based Reconfigurable Processor	Kenta Sasagawa, Tatsuya Nishikawa, Xihong Zhou, Senling Wang, Hiroshi Kai, Hiroshi Takahashi (Ehime Univ.)
Thu, Nov 16 PM Chair: Yoshiki Yamaguchi (Univ. of Tsukuba, Kumamoto Univ.) 13:35 - 14:35
(26) RECONF	13:35-13:45
(27) RECONF	13:45-14:10	A Proposal for Acceleration of FPGA-based Linear Equation Solver using Speculative Execution System	Naoki Kakine, Shuto Yuya, Atsushi Kubota, Tetsuo Hironaka (HCU)
(28) RECONF	14:10-14:35	Hardware obfuscation method using Obfuscator-LLVM and Bambu	Mikiya Ogura, Shuichi Ichikawa (Toyohashi Univ. Tech.)
	14:35-14:50	Break ( 15 min. )
Thu, Nov 16 PM 14:50 - 15:40
(29)	14:50-15:40
	15:40-15:55	Break ( 15 min. )
Thu, Nov 16 PM 15:55 - 17:35
(30) ICD	15:55-16:20	Calculation of Isomorphic/Similar Topology using Graph Theory	Yuto Moriguchi, Nobukazu Takai (KIT)
(31) ICD	16:20-16:45	A multi bit PWM-DAC with calibration for quantum computing	Shunsuke Akahosh, Nobukazu Takai (KIT)
(32) ICD	16:45-17:10	Wearable Perspiration Meter System with 0.18 µm BCD Process and Experimental Investigations for High Precision	Shunsaku Mineo, Ayumu Yamamoto (Shinshu Univ.), Shin-Ichiro Kuroki (Hiroshima Univ.), Hideya Momose (SKINOS), Koh Johguchi (Shinshu Univ.)
(33) ICD	17:10-17:35	Proposed power supply layout for RF circuits with a power panel containing MOM capacitors, bias control lines, and electrostatic protection diodes	Shunto Nishiura, Satoshi Tanaka, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.)
Thu, Nov 16 PM 15:55 - 17:35
(34) DC	15:55-16:20	WGAN-GP based AI accelerator fault detection and fault classification analysis	Shuming Xu, Kazuteru Namba (Chiba Univ.)
(35) DC	16:20-16:45	On Reducing Area Overhead of BIST for Approximate Multiplier Considering Truncated Bits	Daichi Akamatsu, Shougo Tokai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
(36) DC	16:45-17:10	Implementation Evaluation of a Memorism Pattern Matching Accelerator on FPGA	Shion Honda, Tatsuya Nishikawa, Xihong Zhou, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Katsumi Inoue (AOT)
(37) DC	17:10-17:35		Takumi Sugioka, Yosikazu Nagamura (Tokyo Metoropolitan Univ.), Masayuki Arai (Nihon Univ.), Satoshi Fukumoto (Tokyo Metoropolitan Univ.)
Thu, Nov 16 PM 18:00 - 20:00
(38)	18:00-20:00
Fri, Nov 17 AM 09:35 - 10:50
(39) ICD	09:35-10:00	Backside Side-Channel Attack by Silicon Substrate Voltage and Simulation	Rikuu Hasegawa, Kazuki Monta, Takuya Watatsumi, Takuji Miki, Makoto Nagata (Kobe Univ)
(40) ICD	10:00-10:25	Derivation of secret keys by differential fault analysis using backside voltage fault injection	Yusuke Hayashi, Rikuu Hasegawa, Takuya Wadatsumi, Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.)
(41) ICD	10:25-10:50	Analysis for S-parameter differences caused by differences in ground definitions for electromagnetic simulations in high-frequency differential GSSG PADs	Ryotaro Sugimoto, Satoshi Tanaka, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.)
Fri, Nov 17 AM 09:10 - 10:50
(42) VLD	09:10-09:35	Study on the Application of Compressed Sensing Utilizing Random Undersampling to Heart Sound Measurement System	Tomoya Yamamoto, Daisuke Kanemoto, Hirotada Masuda, Tetsuya Hirose (Osaka Univ)
(43) VLD	09:35-10:00	A comparator with variable offset voltage variation by controlling differential pair’s currents	Taira Sakaguchi, Satoshi Komatsu (Tokyo Denki Univ.)
(44) VLD	10:00-10:25	CiM-based Low-bit Neural Network Accelerator Design Method with automatic I/O range optimization	Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi (Univ. of Tokyo)
(45) VLD	10:25-10:50	Low-Latency Hardware Implementation for SPHINCS+ signature generation	Yuta Takeshima, Makoto Ikeda (The Univ. of Tokyo)
	10:50-11:00	Break ( 10 min. )
Fri, Nov 17 AM 11:00 - 11:50
(46)	11:00-11:50	Challenges and measures for increasingly complex semiconductor ○Daisuke Watanabe
	11:50-13:00	Lunch Break ( 70 min. )
Fri, Nov 17 PM 13:00 - 13:20
(47)	13:00-13:20
Fri, Nov 17 PM Chair: Yuichiro Shibata (Nagasaki Univ.) 13:20 - 14:35
(48) RECONF	13:20-13:45	A wafer-scale VLSI realization using optical reconfiguration architecture	Atsushi Takata, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)
(49) RECONF	13:45-14:10	Parallel configuration experiment for a radiation-hardened optically reconfigurable gate array with a holographic polymer-dispersed liquid crystal memory	Sae Goto, Minoru Watanabe (Okayama Univ.), Akifumi Ogiwara (Kobe City College of Technology), Nobuya Watanabe (Okayama Univ.)
(50) RECONF	14:10-14:35	Configuration Data Compression for SLM Fine-grained Reconfigurable Logic	Souhei Takagi, Takuya Kozima, Hideharu Amano (Keio Univ), Morihiro Kuga, Masahiro Iida (Kumamoto Univ)
Fri, Nov 17 PM 13:20 - 14:10
(51)	13:20-13:45
(52)	13:45-14:10
	14:35-14:50	Break ( 15 min. )
Fri, Nov 17 PM Chair: Takefumi Miyoshi (WasaLabo, LLC) 14:50 - 16:30
(53) RECONF	14:50-15:15	Hardware Compression Method Applying Bernoulli Approximation for Bayesian Neural Networks	Taisei Saito, Kota Ando, Tetsuya Asai (Hokkaido Univ.)
(54) RECONF	15:15-15:40	Maximum operating clock frequency evaluation of Mono Instruction Set Computers on an optically reconfigurable gate array VLSI	Soma Imai, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)
(55) RECONF	15:40-16:05	High-Level Synthesis Implementation of a Reservoir Computing based on Chaotic Boltzmann Machine -- Improving scalability and efficiency of sparse matrix multiplication through a dedicated data compression in external memory --	Shigeki Matsumoto, Yuki Ichikawa, Nobuki Kajihara (IVIS), Hakaru Tamukoh (kyutech)
(56) RECONF	16:05-16:30	Study of High-Performance FOC Motor Control using FPGA Processing	Ludi Wang, Takeshi Ohkawa (Kumamoto Univ)
Fri, Nov 17 PM 14:50 - 16:05
(57) VLD	14:50-15:15	An Improved Routing Method by SAT for Set-Pair Routing Problem	Koki Nagakura, Kunihiro Fujiyoshi (TUAT)
(58) VLD	15:15-15:40	Evaluation of the power consumption of the codec chip EG2C for a visual prosthesis	Shogo Hirayama, Naoya Tanaka, Yoshinori Takeuchi (Kindai Univ.)
(59) VLD	15:40-16:05

Announcement for Speakers
General Talk	Each speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD	Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
	Contact Address	Masashi IMAI (Hirosaki Univ. ) E-: bi-u
	Announcement	See also VLD's homepage: http://www.ieice.org/~vld/
ICD	Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
	Contact Address	Kosuke Miyaji (Shinshu University), Takeshi Kuboki (Kumamoto University)
DC	Technical Committee on Dependable Computing (DC) [Latest Schedule]
	Contact Address	Masayuki Arai (College of Industrial Technology, Nihon Univ.) E-: ain-u
RECONF	Technical Committee on Reconfigurable Systems (RECONF) [Latest Schedule]
	Contact Address	Chair: Yoshiki Yamaguchio (Tsukuba Univ.)
	Announcement	RECONF website http://www.ieice.org/~reconf/ RECONF slack https://join.slack.com/t/reconfworkspace/shared_invite/zt-v3qeynk3-RsInu4wdjqU2t_ysqWvagg
IPSJ-SLDM	Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
	Contact Address	Takashi Imagawa (Meiji Univ.) E-: ii
	Announcement	Please see the IPSJ-SLDM page below: http://www.sig-sldm.org/