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| Chair |
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Kazutoshi Wakabayashi (NEC) |
| Vice Chair |
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Atsushi Takahashi (Tokyo Inst. of Tech.) |
| Secretary |
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Ichiro Kohno (Renesas), Nozomu Togawa (Waseda Univ.) |
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| Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) |
[schedule] [select]
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| Chair |
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Shinji Kimura |
| Secretary |
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Takashi Aoki, Naoyuki Hoshi, Kenshu Seto |
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| Conference Date |
Wed, May 20, 2009 14:30 - 16:50
Thu, May 21, 2009 10:00 - 11:55 |
| Topics |
System Design, etc. |
| Conference Place |
Kitakyushu International Conference Center |
| Transportation Guide |
http://www.convention-a.jp/kokusai/access.html |
Contact
Person |
Prof. Yasuhiro Takashima
+81-93-695-3729 |
Wed, May 20 PM System-level Design
Chair: Nozomu Togawa (Waseda Univ.)
14:30 - 15:45 |
(1)
VLD |
14:30-14:55 |
Task Migration for Energy Savings in Multiprocessor Real-Time Systems |
Gang Zeng (Nagoya Univ.), Shinpei Kato (The Univ. of Tokyo), Tetsuo Yokoyama, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.) |
(2)
VLD |
14:55-15:20 |
A Weighted-Sum Circuit Using Selector Logic By Transforming Bit-Level Operations |
Tomoaki Hara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Printing Corp.) |
(3)
VLD |
15:20-15:45 |
A scan test generation method to reduce the number of detected untestable faults |
Hiroshi Ogawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.), Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.) |
| |
15:45-16:00 |
Break ( 15 min. ) |
Wed, May 20 PM Optimizing Algorithms
16:00 - 16:50 |
| (4) |
16:00-16:25 |
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| (5) |
16:25-16:50 |
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Thu, May 21 AM Physical Design
Chair: Ichiro Kohno (Renesas Technology Corp.)
10:00 - 10:50 |
(6)
VLD |
10:00-10:25 |
A RST Construction Method for Vertices with Maximum Path Length |
Masafumi Inoue, Yoichi Tomioka (Tokyo Inst. of Tech.), Yukihide Kohira (the Univ. of Aizu), Atsushi Takahashi (Osaka Univ.) |
(7)
VLD |
10:25-10:50 |
Importance sampling with two-phase preprocess considering structural symmetry of SRAM circuits |
Takanori Date, Shiho Hagiwara, Takumi Uezono (Tokyo Inst. of Tech.), Takashi Sato (Kyoto Univ.), Kazuya Masu (Tokyo Inst. of Tech.) |
| |
10:50-11:05 |
Break ( 15 min. ) |
Thu, May 21 AM Low Power Design
11:05 - 11:55 |
| (8) |
11:05-11:30 |
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| (9) |
11:30-11:55 |
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| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Ichiro Kohno (Renesas Technology Corp.)
E- :  h  i      s
TEL: +81-42-312-5873 |
| Announcement |
See also VLD's homepage:
http://www.ieice.org/~vld/ |
| IPSJ-SLDM |
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
|
| Contact Address |
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Last modified: 2009-05-12 18:11:43
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