| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-17
13:00 |
Kanagawa |
|
Implimentation of high speed audiofingerprint system using FPGAs
Hisashi Isonaga, Yasushi Inoguchi (JAIST) |
In recent year illegal music distribution via network with the file exchange software in recent years becomes a serious ... [more] |
VLD2005-88 CPSY2005-44 RECONF2005-77
pp.1-6 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-17
13:25 |
Kanagawa |
|
Voice Recognition LSI based on FTTSS
Tomotaka Nakano, Park Hu Gang, Tetsuo Funada, Akio Kitagawa (Kanazawa Univ) |
(Advance abstract in Japanese is available) [more] |
VLD2005-89 CPSY2005-45 RECONF2005-78
pp.7-12 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-17
13:50 |
Kanagawa |
|
An LSI design to support Sound Finite Difference Time Domain Method
Daichi Ito, Ryotaro Kobayashi, Toshio Shimada (Nagoya Univ.) |
Recently the FDTD method is used for sound field analysis because it can treat various structures and the procedure to o... [more] |
VLD2005-90 CPSY2005-46 RECONF2005-79
pp.13-18 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-17
14:15 |
Kanagawa |
|
Accelaration of Hydrosynamical Simulations using a FPGA board
Naohito Nakasato, Tsuyoshi Hamada (RIKEN) |
(Advance abstract in Japanese is available) [more] |
VLD2005-91 CPSY2005-47 RECONF2005-80
pp.19-24 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-17
15:00 |
Kanagawa |
|
Programmable Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method
Shinobu Nagayama (Hiroshima City Univ.), Tsutomu Sasao (K.I..T.), Jon T. Butler (Naval Postgraduate School) |
This paper presents an architecture and a synthesis method for programmable numerical function generators
(NFGs) for tr... [more] |
VLD2005-92 CPSY2005-48 RECONF2005-81
pp.25-30 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-17
15:25 |
Kanagawa |
|
Implementation of Stream Application on Programmable Devices by C Level Design
Naohiro Katsura, Yohei Hasegawa, Vu Manh Tuan, Takamasa Kanamori, Hideharu Amano (Keio Univ.) |
While FPGA is a fine grain composition, the Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a... [more] |
VLD2005-93 CPSY2005-49 RECONF2005-82
pp.31-36 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-17
15:50 |
Kanagawa |
|
Multuiple Programming Method and Circuit Design for a Phase Change Nonvolatile Random Access Memory
Takatomi Izumi, Masashi Takata, Kazuya Nakayama, Akio Kitagawa (Kanazawa Univ.) |
A novel multiple programming method for a phase change nonvolatile randamaccess memory(PRAM) is proposed. PRAM uses chal... [more] |
VLD2005-94 CPSY2005-50 RECONF2005-83
pp.37-42 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-17
16:30 |
Kanagawa |
|
Modification of monotonic route to reduce max density for single layer BGA package
Yoshitaka Nomura, Atsushi Takahashi (Tokyo Tech) |
(Advance abstract in Japanese is available) [more] |
VLD2005-95 CPSY2005-51 RECONF2005-84
pp.43-48 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-17
16:55 |
Kanagawa |
|
Boolean Equivalence Checking Using a Subset of First-Order Logic
Atsushi Moritomo, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) |
(Advance abstract in Japanese is available) [more] |
VLD2005-96 CPSY2005-52 RECONF2005-85
pp.49-54 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-18
10:00 |
Kanagawa |
|
Optimization of Body Bias Voltage Set for Threshold Voltage Control in Flex Power FPGA
Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto (AIST), Toshiyuki Tsutsumi (AIST/MEIJI), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
The Flex Power FPGA is a new FPGA architecture which enabled high speed operation and low power-consumption by controlli... [more] |
VLD2005-97 CPSY2005-53 RECONF2005-86
pp.1-6 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-18
10:25 |
Kanagawa |
|
A Study of the Dynamically Reconfigurable Processor Vulcan
Toshihiko Hashinaga (Kyushu Univ.), Lovic Gauthier, Takayuki Kando, Victor Mauro Goulart Ferreira, Ryutaro Susukita (FLEETS), Tetsuo Hiraki, Yosuke Yamazaki, Takaaki Nagano, Kazuaki Murakami (Kyushu Univ.) |
(Advance abstract in Japanese is available) [more] |
VLD2005-98 CPSY2005-54 RECONF2005-87
pp.7-11 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-18
10:50 |
Kanagawa |
|
The direct execution mode on dynamically reconfigurable processors
Hideharu Amano, Yohei Hasegawa, Shohei Abe (Keio Univ.) |
(Advance abstract in Japanese is available) [more] |
VLD2005-99 CPSY2005-55 RECONF2005-88
pp.13-18 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-18
11:15 |
Kanagawa |
|
A Study on Resource Sharing Technique for Multi-Context Logic Device
Hiroshi Shinohara, Masaki Kobata, Shigeki Imai, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
Multi-context reconfigurable devices are convenient solution for runtime reconfiguration. However they suffer from recon... [more] |
VLD2005-100 CPSY2005-56 RECONF2005-89
pp.19-24 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-18
13:00 |
Kanagawa |
|
The Proposal and Verification of FPGA Remote-Reconfiguration
Hiroshi Tanno, Hiroshi Tsubokawa (Tokyo University of Technology) |
(Advance abstract in Japanese is available) [more] |
VLD2005-101 CPSY2005-57 RECONF2005-90
pp.25-30 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-18
13:25 |
Kanagawa |
|
Implementation and Evaluation of Remote Logic Analyzer
Go Saitou, Kazuo Nagata, Hideo Harada, Hidetomo Shibamura, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
Electronic equipments carrying a reconfigurable FPGA have advantages, the functions of which can be changed，upgraded aft... [more] |
VLD2005-102 CPSY2005-58 RECONF2005-91
pp.31-36 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-18
13:50 |
Kanagawa |
|
Retargeting GCC and GNU Toolchain for Extended Instruction Set
Yuji Nagamatsu, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuyuki Hikichi (SRA-KTL) |
While ASIPs (Application Specific Instruction set Processors) are attractive components for embedded systems, constructi... [more] |
VLD2005-103 CPSY2005-59 RECONF2005-92
pp.37-41 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-18
14:30 |
Kanagawa |
|
A Parallel Volume Rendering System implemented with High-Speed DVI Link
Dai Okamura, Yusuke Noda, Shinobu Miwa, Hajime Shimada (Kyoto Univ), Yasuhiko Nakashima (Kyoto Univ/JST), Shin-ichiro Mori, Shinji Tomita (Kyoto Univ) |
(Advance abstract in Japanese is available) [more] |
VLD2005-104 CPSY2005-60 RECONF2005-93
pp.43-46 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-18
14:55 |
Kanagawa |
|
A Stochastic Biochemical Simulator with a Data-transfer Network on an FPGA
Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.) |
A high-perfomance biochemical simulatior using a reconfigurable system draws attention as a low-cost solution from biolo... [more] |
VLD2005-105 CPSY2005-61 RECONF2005-94
pp.47-52 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-18
15:20 |
Kanagawa |
|
A Performance Improvement Strategy for Numerical Integration on an FPGA-Based Biochemical Simulator ReCSiP
Yuri Nishikawa, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Toshinori Kojima (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.) |
Computational simulation is a highly effective solution for cellular analyses in recent bioinformatics. As the scale of... [more] |
VLD2005-106 CPSY2005-62 RECONF2005-95
pp.53-58 |
| RECONF, CPSY, VLD, IPSJ-SLDM |
2006-01-18
15:45 |
Kanagawa |
|
Hardware-resource Utilization Analysis on an FPGA-Based Biochemical Simulator ReCSiP
Yasunori Osana (Keio Univ.), Naoki Iwanaga (Nagasaki Univ.), Masato Yoshimi, Yow Iwaoka, Toshinori Kojima, Yuri Nishikawa (Keio Univ.), Akira Funahashi (JST), Noriko Hiroi (Keio Univ.), Yuichiro Shibata, Hiroaki Kitano (Nagasaki Univ.), Hideharu Amano (Keio Univ.) |
(Advance abstract in Japanese is available) [more] |
VLD2005-107 CPSY2005-63 RECONF2005-96
pp.59-64 |