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Technical Committee on Dependable Computing (DC)
Chair: Nobuyasu Kanekawa (Hitachi) Vice Chair: Michiko Inoue (NAIST)
Secretary: Koji Iwata (RTRI), Masayoshi Yoshimura (Kyoto Sangyo Univ.)
DATE:
Tue, Jun 16, 2015 14:10 - 16:50
PLACE:
TOPICS:
Reliable design and Test, etc.
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Tue, Jun 16 PM (14:10 - 16:50)
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(1) 14:10 - 14:35
A test data reduction method based on scan slice on BAST
Makoto Nishikiori, Hiroshi Yamazaki, Toshinori Hosokawa, Masayuki Arai (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.)
(2) 14:35 - 15:00
Study on Fast Bridge Fault Test Generation Based on Critical Area
Masayuki Arai (Nihon Univ.), Shingo Inuyama, Kazuhiko Iwasaki (Tokyo Metro. Univ.)
(3) 15:00 - 15:25
A Method to Identify High Test Power Areas in Layout Design
Kohei Miyase (Kyutech), Matthias Sauer, Bernd Becker (Univ. Freiburg), Xiaoqing Wen, Seiji Kajihara (Kyutech)
----- Break ( 10 min. ) -----
(4) 15:35 - 16:00
A Study on Function Test of Latch-based Asynchronous Pipeline Circuits
Daiki Toyoshima, Kyohei Terayama, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.)
(5) 16:00 - 16:25
Performance Evaluation of Dependability Improvement Methods for Multiple Core Systems based on Markov Models
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII)
(6) 16:25 - 16:50
Using binary decision diagrams for constraint handling in test case generation
Tatsuhiro Tsuchiya (Osaka Univ.)
# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.
=== Technical Committee on Dependable Computing (DC) ===
# FUTURE SCHEDULE:
Tue, Aug 4, 2015 - Thu, Aug 6, 2015: B-Con Plaza (Beppu) [Fri, May 15], Topics: Parallel, Distributed and Cooperative Processing
Last modified: 2015-04-28 12:48:55
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