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Technical Committee on Integrated Circuits and Devices (ICD)
Chair: Kunio Uchiyama (Hitachi) Vice Chair: Masahiko Yoshimoto (Kobe Univ.), Toshihiko Hamasaki (TI)
Secretary: Yoshio Hirose (Fujitsu Labs.), Hiroaki Suzuki (Renesas)
Assistant: Toshimasa Matsuoka (Osaka Univ.), Ken Takeuchi (Univ. of Tokyo), Kenichi Okada (Tokyo Inst. of Tech.)

DATE:
Mon, Apr 18, 2011 10:00 - 18:55
Tue, Apr 19, 2011 09:30 - 16:40

PLACE:
Kobe University Takigawa Memorial Hall(1-1 Rokkodai-cho, Nada-ku, Kobe 657-8501, Japan. Hanshin "Mikage" station,JR "Rokkomichi" station,Hankyu "Rokko" station Take Kobe City Bus. http://www.kobe-u.ac.jp/en/access/rokko/other-transportation-terminals.htm)

TOPICS:
Memory Device Technologies

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Mon, Apr 18 AM (10:00 - 12:30)
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(1) 10:00 - 10:50
[Invited Talk]
Trends and Multi-level-cell Technology of Spin Transfer Torque Memory
Takashi Ishigaki, Takayuki Kawahara, Riichiro Takemura, Kazuo Ono, Kenchi Ito (Hitachi), Hideo Ohno (Tohoku U.)

(2) 10:50 - 11:40
[Invited Talk]
A Technical Trend and Embedded DRAM Technology for High-Performance NAND Flash Memories
Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii (Toshiba)

(3) 11:40 - 12:30
[Invited Talk]
ReRAM Test Macro with High Speed Read/Program Circuit
-- Conductive Bridge ReRAM with 2.3GB/s Read throughput and 216MB/s Program-throughput --
Keiichi Tsutsui, Wataru Otsuka, Koji Miyata, Makoto Kitagawa, Tomohito Tsushima (Sony)

----- Lunch Break ( 60 min. ) -----

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Mon, Apr 18 PM (13:30 - 18:55)
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(1) 13:30 - 14:20
[Invited Talk]
Technology Trend of NAND Flash Memories
-- A 151mm2 64Gb 2b/cell NAND Flash Memory in 24nm CMOS Technology --
Koichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Junpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Toshiaki Edahiro, Takeshi Ogawa, Makoto Iwai (Toshiba), Kiyofumi Sakurai (Toshiba Memory Systems), Toru Miwa (SanDisk)

(2) 14:20 - 15:10
[Invited Talk]
Highly reliable low power SSD
-- Data modulation signal processing technologies of memory cotroller --
Ken Takeuchi, Shuhei Tanakamaru, Chinglin Hung (Univ. Tokyo)

----- Break ( 10 min. ) -----

(3) 15:20 - 16:10
[Invited Talk]
Trend in Phase Change Memory and activity in TIA
Norikatsu Takaura (LEAP)

(4) 16:10 - 17:00
[Invited Talk]
3-Dimensional NAND Flash memories
Seiichi Aritome (Hynix)

----- Break ( 10 min. ) -----

(5) 17:10 - 18:55

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Tue, Apr 19 AM (09:30 - 12:10)
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(1) 09:30 - 09:55
0.45-V Operating Vt-Variation Tolerant 9T/18T Dual-Port SRAM
Koji Yanagida, Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST), Hiroshi Kawaguchi (Kobe Univ.)

(2) 09:55 - 10:20
A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers
Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe (Toshiba)

(3) 10:20 - 10:45
Multi-step Word-line Control Technology in Hierarchical Cell Architecture for Scaled-down High-density SRAMs
Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Kiyoshi Takeuchi, Masahiro Nomura, Yoshihiro Hayashi (Renesas Electronics)

----- Break ( 10 min. ) -----

(4) 10:55 - 11:20
0.5-V FinFET SRAM Using Dynamic-Threshold-Voltage Pass Gates
Shin-ichi O'uchi, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Tadashi Nakagawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara (AIST)

(5) 11:20 - 11:45
0.5-V, 5.5-nsec Access Time, Bulk-CMOS 8T SRAM with Suspended Bit-Line Read Scheme
Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara (STARC)

(6) 11:45 - 12:10
Suppress of Half Select Disturb in 8T-SRAM by Local Injected Electron Asymmetric Pass Gate Transistor
Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo)

----- Lunch Break ( 60 min. ) -----

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Tue, Apr 19 PM (13:10 - 14:50)
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(7) 13:10 - 14:00
[Invited Talk]
A 12Gb/s Non-Contact Interface with Coupled Transmission Lines
Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.)

(8) 14:00 - 14:25
1-Tbyte/s 1-Gbit Multicore DRAM Architecture using 3-D Integration for High-throughput Computing
Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Tomonori Sekiguchi (Hitachi, CRL)

(9) 14:25 - 14:50
Design of Program-voltage(20V) Booster and TSV for High Speed and Low Power 3-D Solid State Drive System
Teruyoshi Hatanaka, Koh Johguchi, Koichi Ishida, Tadashi Yasufuku, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi (Univ. of Tokyo)

----- Break ( 10 min. ) -----

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Tue, Apr 19 PM (15:00 - 16:40)
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(10) 15:00 - 15:25
Basic memory characteristics of HfO2-CB-RAM
Shigeyuki Tsuruta (Tottori Univ.), Kentaro Kinoshita (Tottori Univ./ TEDREC), Tatsuya Nakabayashi (Tottori Univ.), Satoru Kishida (Tottori Univ./ TEDREC)

(11) 15:25 - 15:50
Physical Analysis on ReRAM Filaments Using Atomic Force Microscope
Takatoshi Yoda (Tottori Univ.), Kentaro Kinoshita, Satoru Kishida (Tottori University/TEDREC), Toshiya Ogiwara, Hideo Iwai, Sei Fukushima, Shigeo Tanuma (NIMS)

(12) 15:50 - 16:15
Switching Mechanism of Perovskite-Oxide-Based Resistive Random Access Memory (ReRAM)
Akihiro Hanada (Tottori Univ.), Kentaro Kinoshita (Tottori Univ./TEDREC), Katsuhiko Matsubara, Takahiro Fukuhara (Tottori Univ.), Satoru Kishida (Tottori Univ./TEDREC)

(13) 16:15 - 16:40
Analyses on Co-relation between Low and High Resistance States in ReRAM Consisting of Binary-Transition-Metal-Oxides
Hayato Tanaka (Tottori Univ), Kentaro Kinoshita, Satoru Kishida (Tottori Univ./TEDREC)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.

# CONFERENCE SPONSORS:
- IEEE SSCS Japan/Kansai Chapter

=== Technical Committee on Integrated Circuits and Devices (ICD) ===
# FUTURE SCHEDULE:

Mon, May 16, 2011 - Wed, May 18, 2011: Kitakyushu International Conference Center [Fri, Mar 11], Topics: LSI and Systems Workshop
Thu, Jul 21, 2011 - Fri, Jul 22, 2011: Hiroshima Institute of Technology [Fri, May 20], Topics: Analog, Mixed analog and digital, RF, and sensor interface circuitry

# SECRETARY:
Ken Takeuchi (The University of Tokyo)
TEL 03-5841-6672,FAX 03-5841-6672
E-mail:icd-