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=============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Kentaro Sano (RIKEN) Vice Chair: Yoshiki Yamaguchi (Tsukuba Univ.), Tomonori Izumi (Ritsumeikan Univ.) Secretary: Yuuki Kobayashi (NEC), Yukinori Sato (Toyohashi Univ. of Tech.) Assistant: Yukitaka Takemura (INTEL), Yasunori Osana (Ryukyu Univ.) DATE: Tue, Jun 7, 2022 13:00 - 17:05 Wed, Jun 8, 2022 09:20 - 17:40 PLACE: Center for Computational Sciences, Tsukuba Univ. and Zoom(1-1-1 Tennodai, Tsukuba, Ibaraki 305-8577) TOPICS: Reconfigurable system, etc. ---------------------------------------- Tue, Jun 7 PM (13:00 - 14:15) ---------------------------------------- (1) 13:00 - 13:25 Accelerating Deep Learning-based Path Planning Method on FPGAs Keisuke Sugiura, Hiroki Matsutani (Keio Univ.) (2) 13:25 - 13:50 Shoin Maeda, Hiroshi Nakamura, Hideki Takase (UT) (3) 13:50 - 14:15 Hardware implementation of the protocol for ROS2 and robot modules without CPU Daiki Matsunaga, Tomoya Shoji, Shozo Takeoka (AXE) ----- Break ( 10 min. ) ----- ---------------------------------------- Tue, Jun 7 PM (14:25 - 16:05) ---------------------------------------- (4) 14:25 - 14:50 Performance Evaluation of Fault-Tolerant Routing Methods Using NAS Parallel Benchmarks Yota Kurokawa, Masaru Fukushi (Yamaguchi Univ.) (5) 14:50 - 15:15 Vector Register Sharing Mechanism for Hardware Acceleration Tomoaki Tanaka, Ryousuke Higashi (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) (6) 15:15 - 15:40 Optically reconfigurable gate array VLSI with a perfect parallel configuration function Sae Goto, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) (7) 15:40 - 16:05 290 Mrad total-ionizing-dose tolerance experiment for an optically reconfigurable gate array VLSI Kaho Yamada, Takeshi Okazaki, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Tue, Jun 7 PM (16:15 - 17:05) ---------------------------------------- (8) 16:15 - 16:25 (See Japanese page.) (9) 16:25 - 16:35 An Implementation of a Pattern-matching Accelerator on a RISC-V Processor Riku Takayama, Jubee Tada (Yamagata Univ.) (10) 16:35 - 16:45 Design of a Quantum Annealing Accelerator for Sparse Ising Model Yuta Ohma, Hasitha Muthumala Waidyasooriya, Masanori Hariyama (Tohoku Univ.) (11) 16:45 - 16:55 Preliminary Evaluation of FPGA-to-FPGA Communication Speed in FPGA Cluster ESSPER Rintaro Sakai, Yasuhiro Nakahara (Kumamoto Univ. /R-CSS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CSS) (12) 16:55 - 17:05 Development of Vehicles GPS Time Synchronized Vibration Measurement System for Bridge Health Monitoring Masaaki Ono, Ryota Shin, Yukihiko Okada, Ryosuke Yamamoto (Univ. of Tsukuba) ----- ( 20 min. ) ----- ---------------------------------------- Wed, Jun 8 AM (09:20 - 10:35) ---------------------------------------- (13) 09:20 - 09:45 Investigation of methods to accelerate inference processing by deep learning Seiya Iwamoto, Chikako Nakanishi (OIT) (14) 09:45 - 10:10 Consideration of speeding up AI inference processing by cooperative operation of hardware and software Tomoya Kawakami, Chikako Nakanishi (OIT) (15) 10:10 - 10:35 (See Japanese page.) ----- Break ( 10 min. ) ----- ---------------------------------------- Wed, Jun 8 AM (10:45 - 12:00) ---------------------------------------- (16) 10:45 - 11:10 (See Japanese page.) (17) 11:10 - 11:35 (See Japanese page.) (18) 11:35 - 12:00 Introduction of Power Monitoring Tool for FPGA Clusters and Power Analysis of FPGA Clusters Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano (Keio Univ) ----- Break ( 120 min. ) ----- ---------------------------------------- Wed, Jun 8 PM (14:00 - 14:50) ---------------------------------------- (19) 14:00 - 14:50 (See Japanese page.) ----- Break ( 10 min. ) ----- ---------------------------------------- Wed, Jun 8 PM (15:00 - 16:15) ---------------------------------------- (20) 15:00 - 15:25 Regularization based CNN Optimizing and the acceleration on FPGA Hengyi Li, Xuebin Yue, Lin Meng (RU) (21) 15:25 - 15:50 A Compact High-Speed CNN Implementation based on Redundant Computational Analysis and FPGA Acceleration Li Qi, Li Hengyi, Meng Lin (Ritsumeikan Univ.) (22) 15:50 - 16:15 Structural Sparsification of Activations and Weights for Low Latency Implementation of CNN Akira Jinguji, Naoto Soga, Hiroki Nakahara (Tokyo Tech) ----- Break ( 10 min. ) ----- ---------------------------------------- Wed, Jun 8 PM (16:25 - 17:40) ---------------------------------------- (23) 16:25 - 16:50 A Parallel Processing of Point Feature Histogram on FPGAs Ryuto Kojima, Keisuke Sugiura, Hiroki Matsutani (Keio Univ.) (24) 16:50 - 17:15 (See Japanese page.) (25) 17:15 - 17:40 (See Japanese page.) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on Reconfigurable Systems (RECONF) === # FUTURE SCHEDULE: Wed, Sep 7, 2022 - Thu, Sep 8, 2022: emCAMPUS STUDIO [Thu, Jul 14], Topics: Reconfigurable system, etc. # SECRETARY: Tomonori IZUMI (Ritsumeikan Univ) E-mail: t-i         i # ANNOUNCEMENT: # RECONF Website http://www.ieice.org/~reconf/ RECONF Slack https://join.slack.com/t/reconfworkspace/shared_invite/zt-v3qeynk3-RsInu4wdjqU2t_ysqWvagg Last modified: 2022-06-08 14:23:19 |
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