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Technical Committee on Reconfigurable Systems (RECONF)
Chair: Hideharu Amano Vice Chair: Nobuki Kajihara, Akira Nagoya
Secretary: Masahiro Iida, Tomonori Izumi
Assistant: Yohei Hori
DATE:
Thu, Sep 20, 2007 13:00 - 17:30
Fri, Sep 21, 2007 09:00 - 17:15
PLACE:
Biwako-Kusatsu Campus, Ritsumeikan University(1-1-1 Noji-Higashi, Kusatsu, Shiga 525-8577, Japan. 10minutes bus from JR Minami-Kusatsu Station. http://www.ritsumei.ac.jp/mng/gl/koho/annai/profile/access/biwa_l.html. Prof. Tomonori IZUMI. 077-561-2814)
TOPICS:
Reconfigurable Systems, etc
----- Opening Address ( 10 min. ) -----
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Thu, Sep 20 PM (13:00 - 14:30)
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(1) 13:00 - 13:30
Proposal and application of Memory with Digit-Width Converter
Yuhki Yamabe, Kazuya Tanigawa, Tetsuo Hironaka (HCU)
(2) 13:30 - 14:00
Implementation of Memory (MPLD) with The Ability to work as a Reconfigurable Device
Masanori Yoshihara, Naoki Hirakawa, Kazuya Tanigawa, Tetsuo Hironaka (HCU), Masayuki Sato (GTI)
(3) 14:00 - 14:30
Consideration about Routing Resources for DS-HIE Architecture
Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (HCU)
----- Break ( 15 min. ) -----
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Thu, Sep 20 PM (14:45 - 16:15)
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(4) 14:45 - 15:15
Multi-context optically reconfigurable gate array
Naoki Yamaguchi, Minoru Watanabe (Shizuoka Univ.)
(5) 15:15 - 15:45
A fast optical reconfiguration under an operation of a gate array in an ODRGA-VLSI
Mao Nakajima, Minoru Watanabe (Shizuoka Univ.)
(6) 15:45 - 16:15
Measurement for reconfiguration and retention time of a dymaic optically reconfigurable architecture
Daisaku Seto, Minoru Watanabe (Shizuoka Univ.)
----- Break ( 15 min. ) -----
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Thu, Sep 20 PM (16:30 - 17:30)
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(7) 16:30 - 17:30
[Invited Talk]
Reconfigurable Architecture for Car Tuners
Makoto Ozone, Katsunori Hirase, Kazuhisa Iizuka, Tatsuo Hiramatsu (SANYO), Shinji Kimura (Waseda Univ.)
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Fri, Sep 21 AM (09:00 - 11:00)
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(8) 09:00 - 09:30
A Study of Performance-driven Simultaneous Clustering and Placement for FPGA
Hiroshi Shinohara, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
(9) 09:30 - 10:00
Hardware/Software Partitioning for SoPC based Embedded Systems
Kenichi Shimada (NEC Electronics), Masaru Fukushi, Susumu Horiguchi (Tohoku Univ.)
(10) 10:00 - 10:30
Dynamically Reconfigurable Protocol Transducer Synthesis for utilizing IPs
Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita (Tokyo Univ.)
(11) 10:30 - 11:00
An Implementation of Operating System Functions for a Reconfigurable System
Akira Kojima, Kazuya Tokunaga, Tetsuo Hironaka (Hiroshima City Univ.)
----- Break ( 15 min. ) -----
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Fri, Sep 21 AM (11:15 - 12:15)
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(12) 11:15 - 12:15
[Special Talk]
Technology Trends in Reconfigurable Logic Circuit
Takayuki Kaneda (JPO)
----- Lunch Break ( 75 min. ) -----
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Fri, Sep 21 PM (13:30 - 15:00)
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(13) 13:30 - 14:00
A Study on Multibyte Processing for NFA-based Pattern Matching Circuits
Norio Yamagaki, Satoshi Kamiya (NEC Corp.)
(14) 14:00 - 14:30
Proposal and Evaluation of the Network-based Stochastic Biochemical Simulator on an FPGA
Masato Yoshimi, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi (Keio Univ.), Noriko Hiroi (EMBL-EBI), Yuichiro Shibata, Hideki Yamada (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.)
(15) 14:30 - 15:00
Pipeline MD5 Implementations on FPGA with Data Forwarding
Hoang Anh Tuan, Katsuhiro Yamazaki, Shigeru Oyanagi (Ritsumeikan Univ)
----- Break ( 15 min. ) -----
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Fri, Sep 21 PM (15:15 - 17:15)
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(16) 15:15 - 15:45
Performance Evaluation of Dynamic-Reconfigurable Processor MuCCRA-1 with Various Applications
Adepu Parimala, Yohei Hasegawa, Vasutan Tunbunheng, Hideharu Amano (Keio Univ.)
(17) 15:45 - 16:15
Dynamic Reconfigurable Processor with direct execution mode
Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio univ)
(18) 16:15 - 16:45
Representing dynamically reconfigurable architectures for placement and routing based on graphs with configuration information
Vasutan Tunbunheng, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.)
(19) 16:45 - 17:15
An Energy Reduction Technique with Dynamic Frequency Scaling Control for Dynamically Reconfigurable Processor Arrays
Satoshi Tsutsumi, Yohei Hasegawa, Takashi Nishimura, Hideharu Amano (Keio Univ.)
----- Closing ( 10 min. ) -----
# CONFERENCE SPONSORS:
- supported by IEEE CS(Computer Society) Kansai Chapter
=== Technical Committee on Reconfigurable Systems (RECONF) ===
# FUTURE SCHEDULE:
Tue, Nov 20, 2007 - Thu, Nov 22, 2007: Kitakyushu International Conference Center [Fri, Sep 14], Topics: Design Gaia 2007 ---A New Frontier in VLSI Design---
# SECRETARY:
Masahiro IIDA (Kumamoto Univ.)
E-mail: ii-u
TEL: +81-96-342-3649 FAX: +81-96-342-3649
Last modified: 2007-08-16 12:13:20
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