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Special Interest Group on System Architecture (IPSJ-ARC)
Chair: Koji Inoue (Kyushu Univ.)
Secretary: Masaaki Kondo (Univ. of Tokyo), Ryota Shioya (Nagoya Univ.), Miho Tanaka (Fujitsu Lab.), Yohei Hasegawa (Toshiba Memory)
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Technical Committee on VLSI Design Technologies (VLD)
Chair: Noriyuki Minegishi (Mitsubishi Electric) Vice Chair: Nozomu Togawa (Waseda Univ.)
Secretary: Koyo Nitta (NTT), Yukihide Kohira (Univ. of Aizu)
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Technical Committee on Computer Systems (CPSY)
Chair: Koji Nakano (Hiroshima Univ.) Vice Chair: Hidetsugu Irie (Univ. of Tokyo), Takashi Miyoshi (Fujitsu)
Secretary: Takeshi Ohkawa (Utsunomiya Univ.), Shinya Takameda (Hokkaido Univ.)
Assistant: Yasuaki Ito (Hiroshima Univ.), Tomoaki Tsumura (Nagoya Inst. of Tech.)
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Technical Committee on Reconfigurable Systems (RECONF)
Chair: Masato Motomura (Hokkaido Univ.) Vice Chair: Yuichiro Shibata (Nagasaki Univ.), Kentaro Sano (RIKEN)
Secretary: Kazuya Tanigawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan)
Assistant: Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.)
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Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)
Chair: Yutaka Tamiya (Fujitsu Lab.)
Secretary: Seiya Shibata (NEC), Yukio Mitsuyama (Kochi Univ. of Tech.), Eiichi Hosoya (NTT)
DATE:
Wed, Jan 30, 2019 10:30 - 20:00
Thu, Jan 31, 2019 09:30 - 16:20
PLACE:
(https://www.keio.ac.jp/en/maps/hiyoshi.html)
TOPICS:
FPGA Applications, etc.
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Wed, Jan 30 AM (10:30 - 12:10)
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(1)/VLD 10:30 - 10:55
On Delay Optimization for Improving General Synchronous Performance
Eijiro Sassa, Shimpei Sato, Atsushi Takahashi (Tokyo Tech)
(2)/VLD 10:55 - 11:20
Proposal of reduction method of calculations by using Leading Zero in the Extended Euclidean Algorithm
Masaki Ogino, Yuki Tanaka, Shugang Wei (Gunma Univ.)
(3)/VLD 11:20 - 11:45
An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults
Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo)
(4) 11:45 - 12:10
(Cancelled)
----- Lunch Break ( 80 min. ) -----
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Wed, Jan 30 PM (13:30 - 14:45)
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(5)/RECONF 13:30 - 13:55
A CNN with a Noise Addition for Efficient Implementation on an FPGA
Atsuki Munakata, Shimpei Satou, Hiroki Nakahara (Tokyo Tech)
(6)/RECONF 13:55 - 14:20
Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation
Masayuki Shimoda, Youki Sada, Hiroki Nakahara (titech)
(7)/RECONF 14:20 - 14:45
Study of stacked full adder circuit with fabrication technology of 3D flash memory
Fumiya Suzuki, Sigeyoshi Watanabe (Shonan Inst. of Tech.)
----- Break ( 20 min. ) -----
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Wed, Jan 30 PM (15:05 - 16:20)
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(8)/RECONF 15:05 - 15:30
Design and implementation of FPGA measurement feedback system in Coherent Ising Machine
Toshimori Honjo, Takahiro Inagaki, Kensuke Inaba, Takuya Ikuta, Hiroki Takesue (NTT)
(9)/RECONF 15:30 - 15:55
An integrated development platform of FPGA for ROS-based autonomous mobile robot
Sou Tamura, Yasuhiro Nitta, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ)
(10)/RECONF 15:55 - 16:20
Implementation of Image Processing Algorithm Aiming for Autonomous Car Using FPGA
Koki Honda, Wei Kaije, Hideharu Amano (Keio Univ.)
----- Break ( 20 min. ) -----
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Wed, Jan 30 PM (16:40 - 17:40)
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(11)/CPSY 16:40 - 17:40
[Invited Talk]
Large Scale PC Cluster Technologies
-- 20 years and future perspectives perspectives --
Kohta Nakashima (Fujitsu lab.)
----- Break ( 20 min. ) -----
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Wed, Jan 30 PM (18:00 - 20:00)
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Thu, Jan 31 AM (09:30 - 10:45)
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(12)/CPSY 09:30 - 09:55
The Evaluation of Partial Reconfiguration for FiCSW
Miho Yamakura, Keita Azegami, Kazusa Musha, Hideharu Amano (Keio Univ.)
(13)/CPSY 09:55 - 10:20
A Deduplication Mechanism for Effectively-once Semantics Using FPGA NIC
Koji Suzuki, Koya Mitsuzuka, Takuma Iwata, Hiroki Matsutani (Keio Univ.)
(14)/CPSY 10:20 - 10:45
Preliminary Evaluation of Parallel Processing Performance on MPI Runtime Environment for Android OS
Masahiro Nissato, Hiroki Sugiyama, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.)
----- Break ( 15 min. ) -----
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Thu, Jan 31 AM (11:00 - 12:15)
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(15)/CPSY 11:00 - 11:25
A Case for Unsupervised Abnormal Behavior Detection Using Multiple Online Sequential Learning Cores
Rei Ito, Mineto Tsukada (Keio Univ), Masaaki Kondo (Univ Tokyo), Hiroki Matsutani (Keio Univ)
(16)/CPSY 11:25 - 11:50
Area and Performance Evaluations of Online Sequential Learning and Unsupervised Anomaly Detection Core
Tomoya Itsubo, Mineto Tsukada, Hiroki Matsutani (Keio Univ.)
(17) 11:50 - 12:15
----- Lunch Break ( 80 min. ) -----
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Thu, Jan 31 PM (13:35 - 14:50)
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(18)/RECONF 13:35 - 14:00
(See Japanese page.)
(19)/RECONF 14:00 - 14:25
Preliminary evaluation of special instruction implementation methods by high level synthesis
Ryodai Iwamoto, Naoki Fujieda, Shuichi Ichikawa, Joji Sakamoto (TUT)
(20)/RECONF 14:25 - 14:50
(See Japanese page.)
----- Break ( 15 min. ) -----
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Thu, Jan 31 PM (15:05 - 16:20)
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(21)/RECONF 15:05 - 15:30
(See Japanese page.)
(22)/RECONF 15:30 - 15:55
Takefumi Miyoshi (TOYOTA ITC)
(23)/RECONF 15:55 - 16:20
An implementation and evaluation of Lattice-Boltzmann Method on Intel Programmable Accelerator Card
Takaaki Miyajima, Tomohiro Ueno, Kentaro Sano (RIKEN)
# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.
# CONFERENCE SPONSORS:
- This conference is supported by IEEE CEDA All Japan Joint Chapter.
=== Special Interest Group on System Architecture (IPSJ-ARC) ===
# FUTURE SCHEDULE:
Sun, Mar 17, 2019 - Mon, Mar 18, 2019: Nishinoomote City Hall (Tanega-shima) [Mon, Jan 14], Topics: ETNET2019
=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:
Wed, Feb 27, 2019 - Sat, Mar 2, 2019: Okinawa Ken Seinen Kaikan [Tue, Dec 18], Topics: Design Technology for System-on-Silicon, Hardware Security, etc.
# SECRETARY:
Koyo Nitta (NTT)
E-mail: t
# ANNOUNCEMENT:
# See also VLD's homepage:
http://www.ieice.org/~vld/
=== Technical Committee on Computer Systems (CPSY) ===
# FUTURE SCHEDULE:
Sun, Mar 17, 2019 - Mon, Mar 18, 2019: Nishinoomote City Hall (Tanega-shima) [Mon, Jan 14], Topics: ETNET2019
# SECRETARY:
Takashi Miyoshi (FUJITSU)
TEL +81-44-754-2931, FAX +81-44-754-2672
E-mail:
CPSY WEB
http://www.ieice.or.jp/iss/cpsy/jpn/
=== Technical Committee on Reconfigurable Systems (RECONF) ===
# SECRETARY:
Masato Motomura(Hokkaido Univ.)
E-mail: isti
# ANNOUNCEMENT:
# http://www.ieice.org/~reconf/
=== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) ===
# FUTURE SCHEDULE:
Sun, Mar 17, 2019 - Mon, Mar 18, 2019: Nishinoomote City Hall (Tanega-shima) [Mon, Jan 14], Topics: ETNET2019
# SECRETARY:
Yukio Mitsuyama (Kochi Univ. of Tech.)
E-mail:o-
# ANNOUNCEMENT:
# Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/
Last modified: 2019-01-30 10:56:56
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