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Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)
Chair: Shinji Kimura
Secretary: Takashi Aoki, Naoyuki Hoshi, Kenshu Seto
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Technical Committee on VLSI Design Technologies (VLD)
Chair: Kazutoshi Wakabayashi (NEC) Vice Chair: Atsushi Takahashi (Tokyo Inst. of Tech.)
Secretary: Ichiro Kohno (Renesas), Nozomu Togawa (Waseda Univ.)
DATE:
Wed, May 20, 2009 14:30 - 16:50
Thu, May 21, 2009 10:00 - 11:55
PLACE:
Kitakyushu International Conference Center(http://www.convention-a.jp/kokusai/access.html. Prof. Yasuhiro Takashima. +81-93-695-3729)
TOPICS:
System Design, etc.
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Wed, May 20 PM System-level Design (14:30 - 15:45)
Chair: Nozomu Togawa (Waseda Univ.)
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(1)/VLD 14:30 - 14:55
Task Migration for Energy Savings in Multiprocessor Real-Time Systems
Gang Zeng (Nagoya Univ.), Shinpei Kato (The Univ. of Tokyo), Tetsuo Yokoyama, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.)
(2)/VLD 14:55 - 15:20
A Weighted-Sum Circuit Using Selector Logic By Transforming Bit-Level Operations
Tomoaki Hara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Printing Corp.)
(3)/VLD 15:20 - 15:45
A scan test generation method to reduce the number of detected untestable faults
Hiroshi Ogawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.), Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.)
----- Break ( 15 min. ) -----
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Wed, May 20 PM Optimizing Algorithms (16:00 - 16:50)
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(4) 16:00 - 16:25
(5) 16:25 - 16:50
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Thu, May 21 AM Physical Design (10:00 - 10:50)
Chair: Ichiro Kohno (Renesas Technology Corp.)
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(6)/VLD 10:00 - 10:25
A RST Construction Method for Vertices with Maximum Path Length
Masafumi Inoue, Yoichi Tomioka (Tokyo Inst. of Tech.), Yukihide Kohira (the Univ. of Aizu), Atsushi Takahashi (Osaka Univ.)
(7)/VLD 10:25 - 10:50
Importance sampling with two-phase preprocess considering structural symmetry of SRAM circuits
Takanori Date, Shiho Hagiwara, Takumi Uezono (Tokyo Inst. of Tech.), Takashi Sato (Kyoto Univ.), Kazuya Masu (Tokyo Inst. of Tech.)
----- Break ( 15 min. ) -----
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Thu, May 21 AM Low Power Design (11:05 - 11:55)
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(8) 11:05 - 11:30
(9) 11:30 - 11:55
=== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) ===
=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:
Wed, Jul 1, 2009 - Thu, Jul 2, 2009: Kushiko-shi Shogai Gakushu Center [Fri, May 15], Topics: Signal processing, LSI, etc.
# SECRETARY:
Ichiro Kohno (Renesas Technology Corp.)
E-mail: his
TEL: +81-42-312-5873
# ANNOUNCEMENT:
# See also VLD's homepage:
http://www.ieice.org/~vld/
Last modified: 2009-05-12 18:11:43
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