ken-system: Advance Program

IEICE Technical Committee Submission System
Advance Program

Online Proceedings
[Sign in]
Tech. Rep. Archives

===============================================
Technical Committee on Reconfigurable Systems (RECONF)
Chair: Moritoshi Yasunaga (Univ. of Tsukuba)
Vice Chair: Shorin Kyo (Renesas), Tetsuo Hironaka (Hiroshima City Univ.)
Secretary: Yohei Hori (AIST), Nobuya Watanabe (Okayama Univ.)
Assistant: Yoshiki Yamaguchi (Univ. of Tsukuba)

DATE:
Mon, Sep 26, 2011 10:45 - 17:30
Tue, Sep 27, 2011 09:00 - 14:35

PLACE:
Center for Embedded Computing Systems, Nagoya University(Center for Embedded Computing Systems, Graduate School of Information Science, Nagoya University, Furo-cho, Chikusa-ku, Nagoya, 464-8603 Japan.http://www.nces.is.nagoya-u.ac.jp/access/index.html. Prof. Shinya Honda, Prof. Chiharu Takei)

TOPICS:
Reconfigurable Systems, etc.

----------------------------------------
Mon, Sep 26 AM (10:45 - 12:00)
----------------------------------------

(1) 10:45 - 11:10
Wavepipelining on A Ultra Low Power Reconfigurable Accelerator CMA-1.
Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (The Univ. of Electro-Communications)

(2) 11:10 - 11:35
Feasibility study of nonvolatile reconfiguralbe device by using a standard CMOS logic process
Shuji Kunimitsu, Mamoru Terauchi, Kazuya Tanigawa, Tetsuo Hironaka (HCU), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN)

(3) 11:35 - 12:00
Low Power Dynamically Reconfigurable Processor with Dual-Vdd/Dual-Vth and its Optimization
Kazuei Hironaka, Hideharu Amano (Keio Univ.)

----- Lunch Break ( 90 min. ) -----

----------------------------------------
Mon, Sep 26 PM (13:30 - 14:45)
----------------------------------------

(4) 13:30 - 13:55
A Novel Cluster Structure based on Input Sharing of LUTs
Toshiya Takahashi, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

(5) 13:55 - 14:20
FPGA placement based on Self-Organized Map
Yasuaki Tomonari, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

(6) 14:20 - 14:45
Development Modeling Compiler and Operation Test for the Hardware Design Generate HDL from UML State Machine Diagram
Daiki Kano, Ryota Yamazaki (Tokai Univ.), Naohiko Shimizu (Tokai Univ./IP ARCH, Inc.)

----- Break ( 20 min. ) -----

----------------------------------------
Mon, Sep 26 PM (15:05 - 16:20)
----------------------------------------

(7) 15:05 - 15:30
Evaluation of Reconfigurable Computer System using Application of Parliamentary System
Takahiro Kajiyama, Akira Kojima, Tetsuo Hironaka (HCU)

(8) 15:30 - 15:55
Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs - Hardware and Reconfiguration Layers
Krzysztof Jozwik, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.)

(9) 15:55 - 16:20
Relocation of Partial Reconfiguration Data for Dynamic Reconfigurable System
Sadaki Usagawa, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)

----- Break ( 20 min. ) -----

----------------------------------------
Mon, Sep 26 PM (16:40 - 17:30)
----------------------------------------

(10) 16:40 - 17:30
[Invited Talk]
Dependability of Automotive Embedded Systems
Hiroaki Takada (Nagoya Univ.)

----------------------------------------
Tue, Sep 27 AM (09:00 - 10:15)
----------------------------------------

(11) 09:00 - 09:25
Case Studies on an FPGA with System-Level Multiprocessor Design Toolset
Seiya Shibata, Yuki Ando, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.)

(12) 09:25 - 09:50
A Design Framework for relieving a HW Bottleneck FPGAs Connected with a High-Speed Data Bus
Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST)

(13) 09:50 - 10:15
A Basic Implementation of LUT-based Dynamic and Partial Reconfiguration from Remote Site
Hiroyuki Kawai (Hamamatsu Photonics), Moritoshi Yasunaga (Tsukuba Univ.)

----- Break ( 20 min. ) -----

----------------------------------------
Tue, Sep 27 AM (10:35 - 11:50)
----------------------------------------

(14) 10:35 - 11:00
Parallel template matching operations on a dynamically reconfigurable vision-chip architecture
Yuichiro Yamaji (Shizuoka Univ.), Hironari Nakada (Primearth EV Energy), Minoru Watanabe, Shoji Kawahito (Shizuoka Univ.)

(15) 11:00 - 11:25
Performance Evaluation of Power Monitoring Programs on Reconfigurable Processor DS-HIE
Kyohei Tao, Takatoshi Tamaoki, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)

(16) 11:25 - 11:50
A proposal of pattern matching techniques using dynamically reconfigurable hardware
Masato Nogami, Nobuya Watanabe, Akira Nagoya (Okayama Univ.)

----- Lunch Break ( 90 min. ) -----

----------------------------------------
Tue, Sep 27 PM (13:20 - 14:35)
----------------------------------------

(17) 13:20 - 13:45
Design and Implementation of Adaptive Viterbi Decoder using Dynamic Reconfigurable System STP Engine
Yuken Kishimoto, Takao Toi, Takaaki Miyajima, Hideharu Amano (Keio Univ.)

(18) 13:45 - 14:10
Performance Comparison of the Pattern-Recognition Hardware Using Data-Direct-Implementation Approach
Yusuke Sato, Moritoshi Yasunaga, Noriyuki Aibe (Univ. of Tsukuba)

(19) 14:10 - 14:35
Variable and Clause Elimination in SAT problems using an FPGA
Masayuki Suzuki, Tsutomu Maruyama (Univ. of Tsukuba)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.

=== Technical Committee on Reconfigurable Systems (RECONF) ===
# FUTURE SCHEDULE:

Mon, Nov 28, 2011 - Wed, Nov 30, 2011: NewWelCity Miyazaki [Thu, Sep 1], Topics: Design Gaia 2010 -New Field of VLSI Design-

# SECRETARY:
Tetsuo Hironaka (Hiroshima City Univ.)
E-mail: