| IEICE Technical Committee Submission System Advance Program |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top | Go Back | Prev SDM Conf / Next SDM Conf | [HTML] / [HTML(simple)] / [TEXT] | [Japanese] / [English] |
|
=============================================== Technical Committee on Silicon Device and Materials (SDM) Chair: Tetsuro Endo (Tohoku Univ.) Vice Chair: Yasuo Nara (Fujitsu Semiconductor) Secretary: Yukinori Ono (NTT), Shintaro Nomura (Univ. of Tsukuba) Assistant: Yoshitaka Sasago (Hitachi) =============================================== Technical Committee on Integrated Circuits and Devices (ICD) Chair: Masahiko Yoshimoto (Kobe Univ.) Vice Chair: Takeshi Yamamura (Fujitsu Labs.) Secretary: Hiroaki Suzuki (Renesas), Toshimasa Matsuoka (Osaka Univ.) Assistant: Ken Takeuchi (Univ. of Tokyo), Osamu Watanabe (Toshiba), Akira Tsuchiya (Kyoto Univ.) DATE: Thu, Aug 25, 2011 09:00 - 17:45 Fri, Aug 26, 2011 09:00 - 17:20 PLACE: Toyama Kenmin-Kaikan(4-18, Shinsougawa, Toyama-Shi, Japan. http://kenminkaikan.com/. Prof. Toshihiro Matsuda. 0766-56-7500（Ext502）, 076-432-3111（OnSite）) TOPICS: Low voltage/low power techniques, novel devices, circuits, and applications ---------------------------------------- Thu, Aug 25 AM (09:00 - 17:45) ---------------------------------------- (1) 09:00 - 09:25 Study of pattern area reduction with 3 dimensional transistor for logic circuit Takahiro Kodama, Shigeyoshi Watanabe (SIT), Yu Hiroshima (Oi Electric) (2) 09:25 - 09:50 Study of pattern area reduction for standard cell with planar and SGT transistor Takahiro Kodama, Shigeyoshi Watanabe (SIT) (3) 09:50 - 10:15 Study of pattern area for reconfigurable logic circuit with DG/CNT transistor Takamichi Hayashi, Shigeyoshi Watanabe (SIT) ----- Break ( 10 min. ) ----- (4) 10:25 - 10:50 Power-Performance Estimation of Datta-Das Spin Transistor Yoshiyuki Kondo, Shigeru Kawanaka, Kanna Adachi (Toshiba) (5) 10:50 - 11:15 Plasma Doping and Laser Spike Annealing Technique for Steep SDE Formation in nano-scale MOSFET Emiko Sugizaki, Toshitaka Miyata, Yasunori Oshima, Akira Hokazono, Kanna Adachi, Kiyotaka Miyano, Hideji Tsujii, Shigeru Kawanaka, Satoshi Inaba, Takaharu Itani, Toshihiko Iinuma, Yoshiaki Toyoshima (Toshiba) (6) 11:15 - 12:00 [Invited Talk] Ferroelectric Random Access Memory -- Fundamentals, recent advancements and future -- Shoichiro Kawashima (FSL) ----- Lunch ( 50 min. ) ----- (7) 12:50 - 13:35 [Invited Talk] Sub-nanowatt Circuit Techniques Enabling Wireless-sensor-node Operation with an Energy Harvester Mamoru Ugajin, Toshishige Shimamura, Hiroki Morimura, Shin'ichiro Mutoh, Mitsuru Harada (NTT) (8) 13:35 - 14:20 [Invited Talk] A Wireless Self-powered Sensor with Ambient Energy Sources Takakuni Douseki (Ritsumeikan Univ.) ----- Break ( 10 min. ) ----- (9) 14:30 - 14:55 A Low Power 90-nm CMOS Motion Estimation Processor Array Implementing Stick-shaped Search Window (SSW) Block Matching Algorithm Tadayoshi Enomoto (Chuo Univ.) (10) 14:55 - 15:20 Novel power reduction technique for ReRAM with the automatic evasion circuit of the wasteful overwrite Takaya Handa, Kazuya Nakayama, Akio Kitagawa, Junichi Akita (Kanazawa Univ.) (11) 15:20 - 16:05 [Invited Talk] Applications/Market Trends of Energy Harvesting Keiji Takeuchi (NTT Data Institute of Management Consulting) ----- Break ( 10 min. ) ----- (12) 16:15 - 17:45 [Panel Discussion] Ultralow-power technologies for energy harvesting sensor network systems Keiji Takeuchi (NTT Data BR), Mamoru Ugajin (NTT), Syouichirou Kawasaki (Fujitsu), Takakuni Douseki (Ritsu), Makoto Takamiya (U-Tokyo), Jiro Ida, Yuichi Kado (KIT) ---------------------------------------- Fri, Aug 26 AM (09:00 - 17:20) ---------------------------------------- (13) 09:00 - 09:25 Evaluation of Variability in High-k/Metal-Gate MOSFET using Takeuchi Plot Tomoko Mizutani, Anil Kumar (Univ. of Tokyo), Akio Nishida, Kiyoshi Takeuchi, Satoshi Inaba, Shiro Kamohara (MIRAI-Selete), Kazuo Terada (Hiroshima City Univ.), Tohru Mogami (MIRAI-Selete), Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete) (14) 09:25 - 09:50 Statistical Analysis of DIBL and Current-Onset Voltage (COV) Variability in Scaled MOSFETs Anil Kumar, Tomoko Mizutani (Univ. of Tokyo), Akio Nishida, Kiyoshi Takeuchi, Satoshi Inaba, Shiro Kamohara (MIRAI-Selete), Kazuo Terada (Hiroshima City Univ.), Tohru Mogami (MIRAI-Selete), Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete) (15) 09:50 - 10:15 Phase-change memory driven by poly-Si MOS transistor with low cost and high-programming throughput Yoshitaka Sasago, Masaharu Kinoshita, Hiroyuki Minemura, Yumiko Anzai, Mitsuharu Tai, Kenzo Kurotsuchi, Seiichi Morita, Toshikazu Takahashi, Takashi Takahama, Tadao Morimoto, Toshiyuki Mine, Akio Shima, Takashi Kobayashi (Hitachi) ----- Break ( 10 min. ) ----- (16) 10:25 - 11:10 [Invited Talk] Status and Prospect of Ultra Low Power Logic Devices Jiro Ida (KIT) (17) 11:10 - 11:55 [Invited Talk] Technology Trends in Low Power Digital Circuits Masaya Sumita (Panasonic) ----- Lunch ( 60 min. ) ----- (18) 12:55 - 13:40 [Invited Talk] 0.5V Extremely Low Power Circuits for Wireless Sensor Nodes with Energy Harvesting Makoto Takamiya, Koichi Ishida, Hiroshi Fuketa (Univ. of Tokyo), Masahiro Nomura, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) (19) 13:40 - 14:05 Ultra low noise in-substrate-bitline sense amplifier for 4F2 DRAM array Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Kazuo Ono, Riichiro Takemura (Hitachi) (20) 14:05 - 14:30 Sense Amplifier with Current Control Switch for Small-sized 0.5-V Gigabit-DRAM Arrays Akira Kotabe, Yoshimitsu Yanagawa, Riichiro Takemura, Tomonori Sekiguchi, Kiyoo Itoh (Hitachi) ----- Break ( 10 min. ) ----- (21) 14:40 - 15:05 Dependable SRAM with Enhanced Read-/Write-Margins by Fine-Grained Assist Bias Control for Low-Voltage Operation Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto (Renesas) (22) 15:05 - 15:30 A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue Yuichiro Ishii, Hidehiro Fujiwara, Koji Nii (Renesas Electronics), Hideo Chigasaki, Osamu Kuromiya, Tsukasa Saiki (Renesas Design), Atsushi Miyanishi, Yuji Kihara (Renesas Electronics) (23) 15:30 - 15:55 A Dynamic body-biased SRAM with Asymmetric Halo Implant MOSFETs Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Koji Maekawa, Motoshige Igarashi, Koji Nii (Renesas) ----- Break ( 10 min. ) ----- (24) 16:05 - 16:30 Reduction of Minimum Operating Voltage (VDDmin) of CMOS Logic Circuits with Post-Fabrication Automatically Selective Charge Injection Kentaro Honda, Katsuyuki Ikeuchi (Univ. of Tokyo), Masahiro Nomura (STARC), Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo) (25) 16:30 - 16:55 Energy Efficiency Increase of Integer Unit Enabled by Contention-less Flip-Flops (CLFF) and Separated Supply Voltage between Flip-Flops and Combinational Logics Hiroshi Fuketa (Univ. of Tokyo), Koji Hirairi (STARC), Tadashi Yasufuku, Makoto Takamiya (Univ. of Tokyo), Masahiro Nomura, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo) (26) 16:55 - 17:20 Optimization of the low voltage operation Circuits for the Self-synchronous system Ayumi Kamitani, Makoto Ikeda (Tokyo Univ.) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. Invited Talk will have 40 minutes for presentation and 5 minutes for discussion. === Technical Committee on Silicon Device and Materials (SDM) === # FUTURE SCHEDULE: Thu, Oct 20, 2011 - Fri, Oct 21, 2011: Tohoku Univ. (Niche) [Fri, Aug 19], Topics: Process science and new process technologies Thu, Nov 10, 2011 - Fri, Nov 11, 2011: Kikai-Shinko-Kaikan Bldg. [Mon, Sep 12], Topics: Process, Device, Circuit Simulations, etc # SECRETARY: Yukinori Ono(NTT) Tel 046-240-2641 Fax 046-240-4317 E-mail: o          === Technical Committee on Integrated Circuits and Devices (ICD) === # FUTURE SCHEDULE: Thu, Sep 1, 2011 - Fri, Sep 2, 2011: Riken-Kobe-Institute Mon, Oct 24, 2011 - Tue, Oct 25, 2011: Ｉｃｈｉｎｏｂｏ(Sendai) [Thu, Aug 18] Mon, Nov 28, 2011 - Wed, Nov 30, 2011: NewWelCity Miyazaki [Thu, Sep 1], Topics: Design Gaia 2010 -New Field of VLSI Design- # SECRETARY: Minoru Fujishima (The University of Tokyo) TEL 03-5841-7425,FAX 03-5841-8575 E-mail:   eetu-  Last modified: 2011-08-11 19:31:35 |
Notification: Mail addresses are partially hidden against SPAM.
[Download Paper's Information (in Japanese)] <-- Press download button after click here.
[Cover and Index of IEICE Technical Report by Issue]
[Presentation and Participation FAQ] (in Japanese)
[Return to SDM Schedule Page] / [Return to ICD Schedule Page] /
| Go Top | Go Back | Prev SDM Conf / Next SDM Conf | [HTML] / [HTML(simple)] / [TEXT] | [Japanese] / [English] |
[Return to Top Page]