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=============================================== Technical Committee on Silicon Device and Materials (SDM) Chair: Tetsuro Endo (Tohoku Univ.) Vice Chair: Yasuo Nara (Fujitsu Semiconductor) Secretary: Yukinori Ono (NTT), Shintaro Nomura (Univ. of Tsukuba) Assistant: Yoshitaka Sasago (Hitachi) DATE: Thu, Nov 10, 2011 10:00 - 15:30 Fri, Nov 11, 2011 10:00 - 17:00 PLACE: TOPICS: Process, Device, Circuit Simulations, etc ---------------------------------------- Thu, Nov 10 AM (10:00 - 11:45) ---------------------------------------- ----- Opening Talk ( 5 min. ) ----- (1) 10:05 - 10:55 [Invited Talk] Equivalent circuit models for MEMS sensors and actuators based on electrical circuit simulator Hiroshi Toshiyoshi (Univ. of Tokyo) (2) 10:55 - 11:45 [Invited Talk] SISPAD 2011 Review Hirokazu Hayashi (Lapis Semi.) ----- Lunch Break ( 75 min. ) ----- ---------------------------------------- Thu, Nov 10 PM (13:00 - 15:30) ---------------------------------------- (3) 13:00 - 13:50 [Invited Talk] Phase-change memoy driven by poly-Si transistor enabling three-dimensional stacking Yoshitaka Sasago, Masaharu Kinoshita, Hiroyuki Minemura, Yumiko Anzai, Mitsuharu Tai, Kenzo Kurotsuchi, Seiichi Morita, Toshikazu Takahashi, Takashi Takahama, Tadao Morimoto, Toshiyuki Mine, Akio Shima, Takashi Kobayashi (Hitachi) (4) 13:50 - 14:40 [Invited Talk] Comprehensive Understanding of Random Telegraph Noise with Physics Based Simulation Yusuke Higashi, Nobuyuki Momo, Hisayo S. Momose, Tatsuya Ohguro, Kazuya Matsuzawa (Toshiba) (5) 14:40 - 15:30 [Invited Talk] Device Simulation of STM Carrier Profiling Koichi Fukuda, Masayasu Nishizawa, Tetsuya Tada (AIST), Leonid Bolotov (Tsukuba Univ.), Kaina Suzuki, Shigeo Sato (Fujitsu Semiconductor), Hiroshi Arimoto, Toshihiko Kanayama (AIST) ---------------------------------------- Fri, Nov 11 AM (10:00 - 11:40) ---------------------------------------- (6) 10:00 - 10:25 Simulation of Phonon Transport in Silicon Nanostructures Based on Monte-Carlo Method Kentaro Kukita (Osaka Univ.), Yoshinari Kamakura (Osaka Univ./JST) (7) 10:25 - 10:50 Comparisons of Ballistic Device Performances of Si Nanowire and InAs Nanowire FETs based on First-Principles Band Structure Calculation Naoya Takiguchi, Shunsuke Koba, Hideaki Tsuchiya, Matsuto Ogawa (Kobe Univ.) (8) 10:50 - 11:15 Analytical Compact Model Using Perturbation Method for Circuit Simulation of Ballistic and Quasi-ballistic Gate-All-Around MOSFET with Cylindrical Cross Section He Cheng (Nagoya Univ.), Shigeyasu Uno (Ritsumeikan Univ.), Tatsuhiro Numata, Kazuo Nakazato (Nagoya Univ.) (9) 11:15 - 11:40 Enhancement of current density in asymmetric horn-shaped channel -- Ensemble Monte-Carlo/Molecular Dynamics Simulation -- Takefumi Kamioka (Waseda Univ./JST), Hiroya Imai (Waseda Univ.), Kenji Ohmori, Kenji Shiraishi (Univ. of Tsukuba/JST), Yoshinari Kamakura (Osaka Univ./JST), Takanobu Watanabe (Waseda Univ./JST) ----- Lunch Break ( 80 min. ) ----- ---------------------------------------- Fri, Nov 11 PM (13:00 - 15:05) ---------------------------------------- (10) 13:00 - 13:50 [Invited Talk] Usages of TCAD simulation on development of semiconductor for vehicles and future ploblems Hisashi Ishimabushi, Takashi Ueta, Masaru Nagao, Kimimori Hamada (TMC) (11) 13:50 - 14:15 Investigation of Scaling Limit Due to Short Channel Effects and Channel Boosting Leakage in Bulk and SOI NAND Flash Memory Cells Kousuke Miyaji, Chinglin Hung, Ken Takeuchi (Univ. of Tokyo) (12) 14:15 - 14:40 Design of a Fully-Parallel High-Density Nonvolatile TCAM Using MTJ Devices Akira Katsumata, Shoun Matsunaga, Takahiro Hanyu (Tohoku Univ.) (13) 14:40 - 15:05 Design Technology of stacked Type Chain PRAM Sho Kato, Shigeyoshi Watanabe (SIT) ----- Break ( 15 min. ) ----- ---------------------------------------- Fri, Nov 11 PM (15:20 - 17:00) ---------------------------------------- (14) 15:20 - 15:45 Gate Voltage Dependence of Channel Length Modulation Coefficient for Nanoscale MOSFETs Akira Hiroki, Jong Chul Yoon (Kyoto Institute of Tech.) (15) 15:45 - 16:10 Higher-order Effects of Source and Drain Parasitic Resistances for Nanoscale MOSFETs Jong Chul Yoon, Akira Hiroki (Kyoto Institute of Tech.) (16) 16:10 - 16:35 An Efficient Analysis of Large-Scale RLC Circuits with CMOS Loads Yuichi Tanji (Kagawa Univ.) (17) 16:35 - 17:00 Study of pattern area reduction for standard cell with planar and SGT transistor Takahiro Kodama, Shigeyoshi Watanabe (SIT) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. # CONFERENCE SPONSORS: - This conference is co-sponsored by The Japan Society of Applied Physics. === Technical Committee on Silicon Device and Materials (SDM) === # FUTURE SCHEDULE: Fri, Dec 16, 2011: NAIST [Fri, Oct 14], Topics: Fabrication and Evaluation of Silicon related Materials Tue, Feb 7, 2012 - Wed, Feb 8, 2012: [Tue, Nov 15] # SECRETARY: Yukinori Ono(NTT) Tel 046-240-2641 Fax 046-240-4317 E-mail: o          Last modified: 2011-10-13 09:07:14 |
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