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=============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Akira Onozawa (NTT) Vice Chair: Kimiyoshi Usami (Shibaura Inst. of Tech.) Secretary: Akihisa Yamada (Sharp), Kazutoshi Kobayashi (Kyoto Inst. of Tech.) DATE: Mon, Sep 27, 2010 14:00 - 17:30 Tue, Sep 28, 2010 10:00 - 16:15 PLACE: Kyoto Institute of Technology(Matsugasakihashigami-cho, Sakyou-ku, Kyoto 606-8585 Japan. Take the “Kokusai Kaikan” bound Karasuma Line Subway to “Matsugasaki” Station, and walk east for about 8 min.http://www.kit.ac.jp/01/01_110000.html. Prof. Kazutoshi Kobayashi. +81-75-724-7452) TOPICS: Physical design, etc ---------------------------------------- Mon, Sep 27 PM (14:00 - 15:15) ---------------------------------------- (1) 14:00 - 14:25 Ordered Coloring for Skew Adjustability-Aware Resource Binding Mineo Kaneko (JAIST) (2) 14:25 - 14:50 Accelerator-Centric Task Allocation Based on Algorithm Transformation for Heterogeneous Multicore Processors Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Michitaka Kameyama (Tohoku Univ.) (3) 14:50 - 15:15 Design and Evaluation of Arbiter Physical Unclonable Functions Kota Furuhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, Takeshi Fujino (Ritsumeikan Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Mon, Sep 27 PM (15:30 - 17:30) ---------------------------------------- (4) 15:30 - 16:30 [Invited Talk] Analog Circuit Optimization Using Pareto-Optimality Yu Liu, Masato Yoshioka, Katsumi Homma, Yuzi Kanazawa (Fujitsu Labs), Toshiyuki Shibuya (Fujitsu Labs of America) (5) 16:30 - 17:00 [Invited Talk] An Automatic Test Generation Framework for Digitally-Assisted Analog Circuit Satoshi Komatsu, Mohamed Abbas (Univ. of Tokyo), Yasuo Furukawa (Advantest), Kunihiro Asada (Univ. of Tokyo) (6) 17:00 - 17:30 [Invited Talk] Length Matching Routing on Single Layer for PCB Routing Design Yukihide Kohira (UoA), Atsushi Takahashi (Osaka Univ.) ---------------------------------------- Tue, Sep 28 AM (10:00 - 11:40) ---------------------------------------- (7) 10:00 - 10:25 A Method of Analog IC Placement with Common Centroid Constraints Keitaro Ue, Kunihiro Fujiyoshi (TUAT) (8) 10:25 - 10:50 Analog Layout Retargeting with Constraint Extraction by Matching of Fundamental Circuit Components and Layout Regularity Kazuhiko Shibata, Shigetoshi Nakatake (Univ. of Kitakyushu) (9) 10:50 - 11:15 Regularity-Oriented Compaction with Z-cut Perturbation Shigetoshi Nakatake (Univ. of Kitakyushu) (10) 11:15 - 11:40 Fast Optimization on Minimum Perturbation Placement Realization Yuki Kouno, Yasuhiro Takashima (Univ. of Kitakyushu), Atsushi Takahashi (Osaka Univ.) ----- Break ( 100 min. ) ----- ---------------------------------------- Tue, Sep 28 PM (13:20 - 14:20) ---------------------------------------- (11) 13:20 - 14:20 [Invited Talk] Application of Ultra Low-power Circuit Techniques to Wireless Terminals in Wide Area Ubiquitous Network -- Approach to Nano-watt Wireless Sensor Nodes -- Yuichi Kado (Kyoto Inst. of Tech.), Mitsuru Harada, Mamoru Ugajin, Akihiro Yamagishi, Mitsuo Nakamura (NTT) ----- Break ( 15 min. ) ----- ---------------------------------------- Tue, Sep 28 PM (14:35 - 16:15) ---------------------------------------- (12) 14:35 - 15:00 A study of temperature characteristics of ring-oscillator based threshold voltage estimation Takumi Uezono, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) (13) 15:00 - 15:25 Analysis and Evaluation of Simultaneous Switching Noise of FPGA Yo Takahashi, Toshio Sudo (SIT), Kunio Ota, Kazuhisa Matsuge (Toshiba) (14) 15:25 - 15:50 Measurement Circuits for Acquiring SET PulseWidth Distribution with Fine Time Resolution Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ.) (15) 15:50 - 16:15 Modeling of Latching Probability of Soft-Error-Induced Pulse Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga (Kyusyu Univ.) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Mon, Nov 29, 2010 - Wed, Dec 1, 2010: Kyushu University [Fri, Sep 10], Topics: Design Gaia 2010 ―New Field of VLSI Design― # SECRETARY: Akihisa Yamada (Sharp) E-mail:     a    s rp Tel: +81-743-65-2531, Fax: +81-743-65-0554 # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ Last modified: 2010-09-17 12:43:03 |
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