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Technical Committee on Reconfigurable Systems (RECONF) (Searched in: 2007)
Search Results: Keywords 'from:2007-09-20 to:2007-09-20'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF | 2007-09-20 13:00 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Proposal and application of Memory with Digit-Width Converter Yuhki Yamabe, Kazuya Tanigawa, Tetsuo Hironaka (HCU)  RECONF2007-15 |
We research to enhance the performance of the dynamic reconfigurable processor by reducing the needs of dynamic reconfig... [more] | RECONF2007-15 pp.1-6 |
| RECONF | 2007-09-20 13:30 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Implementation of Memory (MPLD) with The Ability to work as a Reconfigurable Device Masanori Yoshihara, Naoki Hirakawa, Kazuya Tanigawa, Tetsuo Hironaka (HCU), Masayuki Sato (GTI) RECONF2007-16 |
In recent years, FPGAs have been used as a reconfigurable device.As a problem of FPGAs, we cannot use FPGAs as one large... [more] | RECONF2007-16 pp.7-12 |
| RECONF | 2007-09-20 14:00 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Consideration about Routing Resources for DS-HIE Architecture Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka (HCU) RECONF2007-17 |
We have developed DS-HIE architecture which is a dynamic reconfigurable architecture for data streaming applications. I... [more] |
RECONF2007-17 pp.13-18 |
| RECONF | 2007-09-20 14:45 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Multi-context optically reconfigurable gate array Naoki Yamaguchi, Minoru Watanabe (Shizuoka Univ.) RECONF2007-18 |
(Advance abstract in Japanese is available) [more] | RECONF2007-18 pp.19-22 |
| RECONF | 2007-09-20 15:15 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | A fast optical reconfiguration under an operation of a gate array in an ODRGA-VLSI Mao Nakajima, Minoru Watanabe (Shizuoka Univ.) RECONF2007-19 |
(Advance abstract in Japanese is available) [more] | RECONF2007-19 pp.23-27 |
| RECONF | 2007-09-20 15:45 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Measurement for reconfiguration and retention time of a dymaic optically reconfigurable architecture Daisaku Seto, Minoru Watanabe (Shizuoka Univ.) RECONF2007-20 |
(Advance abstract in Japanese is available) [more] | RECONF2007-20 pp.29-33 |
| RECONF | 2007-09-20 16:30 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | [Invited Talk]
Reconfigurable Architecture for Car Tuners Makoto Ozone, Katsunori Hirase, Kazuhisa Iizuka, Tatsuo Hiramatsu (SANYO), Shinji Kimura (Waseda Univ.) RECONF2007-21 |
In car tuner LSIs, the reception processing is expected to be realized by software. Therefore, a new processor suitable ... [more] | RECONF2007-21 pp.35-40 |
| RECONF | 2007-09-21 09:00 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | A Study of Performance-driven Simultaneous Clustering and Placement for FPGA Hiroshi Shinohara, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-22 |
FPGA has a rich flexibility to emulate various circuits, and their performance depend on design tools. In this paper，we... [more] |
RECONF2007-22 pp.41-46 |
| RECONF | 2007-09-21 09:30 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Hardware/Software Partitioning for SoPC based Embedded Systems Kenichi Shimada (NEC Electronics), Masaru Fukushi, Susumu Horiguchi (Tohoku Univ.) RECONF2007-23 |
(Advance abstract in Japanese is available) [more] | RECONF2007-23 pp.47-52 |
| RECONF | 2007-09-21 10:00 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Dynamically Reconfigurable Protocol Transducer Synthesis for utilizing IPs Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita (Tokyo Univ.) RECONF2007-24 |
Protocol transducer synthesis is one of the most important issues for efficient IP core reuse in SoC designs. We propo... [more] |
RECONF2007-24 pp.53-58 |
| RECONF | 2007-09-21 10:30 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | An Implementation of Operating System Functions for a Reconfigurable System Akira Kojima, Kazuya Tokunaga, Tetsuo Hironaka (Hiroshima City Univ.) |
Reconfigurable devices have flexible hardware structures and realize high performance with parallelism. Reconfigurable s... [more] | |
| RECONF | 2007-09-21 11:15 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | [Special Talk]
Technology Trends in Reconfigurable Logic Circuit Takayuki Kaneda (JPO) RECONF2007-25 |
Japan patent office has published patent technology trends survey. We picked up the reconfigurable logic circuit last y... [more] |
RECONF2007-25 pp.59-64 |
| RECONF | 2007-09-21 13:30 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | A Study on Multibyte Processing for NFA-based Pattern Matching Circuits Norio Yamagaki, Satoshi Kamiya (NEC Corp.) RECONF2007-26 |
(Advance abstract in Japanese is available) [more] | RECONF2007-26 pp.65-70 |
| RECONF | 2007-09-21 14:00 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Proposal and Evaluation of the Network-based Stochastic Biochemical Simulator on an FPGA Masato Yoshimi, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi (Keio Univ.), Noriko Hiroi (EMBL-EBI), Yuichiro Shibata, Hideki Yamada (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.) |
(Advance abstract in Japanese is available) [more] | |
| RECONF | 2007-09-21 14:30 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Pipeline MD5 Implementations on FPGA with Data Forwarding Hoang Anh Tuan, Katsuhiro Yamazaki, Shigeru Oyanagi (Ritsumeikan Univ) RECONF2007-27 |
(Advance abstract in Japanese is available) [more] | RECONF2007-27 pp.71-76 |
| RECONF | 2007-09-21 15:15 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Performance Evaluation of Dynamic-Reconfigurable Processor MuCCRA-1 with Various Applications Adepu Parimala, Yohei Hasegawa, Vasutan Tunbunheng, Hideharu Amano (Keio Univ.) RECONF2007-28 |
(Advance abstract in Japanese is available) [more] | RECONF2007-28 pp.77-82 |
| RECONF | 2007-09-21 15:45 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Dynamic Reconfigurable Processor with direct execution mode Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio univ) RECONF2007-29 |
Multi-context dynamically reconfigurable processors require configuration data in the context memory to execute. It m... [more] |
RECONF2007-29 pp.83-88 |
| RECONF | 2007-09-21 16:15 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | Representing dynamically reconfigurable architectures for placement and routing based on graphs with configuration information Vasutan Tunbunheng, Yohei Hasegawa, Satoshi Tsutsumi, Hideharu Amano (Keio Univ.) RECONF2007-30 |
For developing design environment for various types of Dynamically Reconfigurable Processor Arrays (DRPAs), the GCI (... [more] |
RECONF2007-30 pp.89-94 |
| RECONF | 2007-09-21 16:45 |
Shiga | Ritsumeikan Univ. Biwako Kusatsu Campus (Shiga) | An Energy Reduction Technique with Dynamic Frequency Scaling Control for Dynamically Reconfigurable Processor Arrays Satoshi Tsutsumi, Yohei Hasegawa, Takashi Nishimura, Hideharu Amano (Keio Univ.) RECONF2007-31 |
(Advance abstract in Japanese is available) [more] | RECONF2007-31 pp.95-100 |
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