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| Chair |
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Toshinori Hosokawa (Nihon Univ.) |
| Vice Chair |
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Masayuki Arai (Nihon Univ.) |
| Secretary |
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Hideyuki Ichihara (Hiroshima City Univ.), Mamoru Ohara (TIRI) |
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| Conference Date |
Tue, Feb 18, 2025 10:30 - 16:30 |
| Topics |
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| Conference Place |
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Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on DC. |
Tue, Feb 18 AM
10:30 - 11:45 |
| (1) |
10:30-10:55 |
Fault-Tolerant Adaptive Routing Algorithm for Mesh Network Based on the Area-Based Approach and Turn Model  DC2024-106 |
Yasuuyki Miura, Naohisa Fukase (SIT), Tsukasa-Pierre Nakao (JAIST) |
| (2) |
10:55-11:20 |
A Heuristic Algorithm of Design for Diagnosability Based on Don't Care Filling of Control Signals DC2024-107 |
Yui Otsuka, Toshinori Hosokawa (Nihon Univ.), Kouji Yamazaki (Meiji Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) |
| (3) |
11:20-11:45 |
DC2024-108 |
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- |
Break |
Tue, Feb 18 PM
13:15 - 14:30 |
| (4) |
13:15-13:40 |
Reliable Memristor-Based Neural Networks with Fault-Injected Training DC2024-109 |
Md. Sihabul Islam, Ryota Eguchi, Michiko Inoue (NAIST) |
| (5) |
13:40-14:05 |
Feature Analysis for Machine Learning based Test Point Insertion DC2024-110 |
Shoya Sasaki, Akitaka Ide, Senling Wang, Hiroshi Kai, Hiroshi Takahashi (Ehime Univ.) |
| (6) |
14:05-14:30 |
DC2024-111 |
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- |
Break |
Tue, Feb 18 PM
14:40 - 15:55 |
| (7) |
14:40-15:05 |
An Approach to High-Level Synthesis with Hard Error Resilience DC2024-112 |
Asahi Noma, Satoshi Ohtake (Oita Univ.) |
| (8) |
15:05-15:30 |
A C-Element-Based Latch Design for Flip-Flops with Complete SNU and Partial DNU Tolerance and Enhanced Soft Error Resilience Around Clock Edges DC2024-113 |
Song Wang, Kazuteru Namba (Chiba Univ) |
| (9) |
15:30-15:55 |
A Status Signal Sequence Generation Method to Improve Optimistically Estimated Field Random Testability DC2024-114 |
Kyosuke Hirose, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) |
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Break |
Tue, Feb 18 PM
16:05 - 16:30 |
| (10) |
16:05-16:30 |
Low Power ΔΣ Modulator With Low Voltage OTA for Wearable Applications and its measurement results DC2024-115 |
Naoya Maruyama, Satoshi Komatsu (Tokyo Denki Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| DC |
Technical Committee on Dependable Computing (DC) [Latest Schedule]
|
| Contact Address |
Hideyuki Ichihara (Graduate School of Information Sciences, Hiroshima City University)
E- : i        -cu |
Last modified: 2025-01-24 12:17:42
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